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Merge tag 'reset-for-v5.8' of git://git.pengutronix.de/pza/linux into arm/drivers
Reset controller updates for v5.8 This tag adds support for i.MX8MP and i.MX8MN SoCs to the i.MX7 reset controller driver, extends the Hi6220 reset driver to support the AO reset controller used to bring the Mali450 GPU out of reset, and adds a define for the internal DAC reset line on Amlogic GXL SoCs. * tag 'reset-for-v5.8' of git://git.pengutronix.de/pza/linux: reset: hi6220: Add support for AO reset controller reset: imx7: Add support for i.MX8MP SoC dt-bindings: reset: imx7: Document usage on i.MX8MP SoC dt-bindings: reset: imx7: Add support for i.MX8MN dt-bindings: reset: meson: add gxl internal dac reset Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2 parents 93f9fb1 + 697fa27 commit 0417a5c

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6 files changed

+253
-31
lines changed

6 files changed

+253
-31
lines changed

‎Documentation/devicetree/bindings/reset/fsl,imx7-src.txt

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,8 @@ Required properties:
99
- For i.MX7 SoCs should be "fsl,imx7d-src", "syscon"
1010
- For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon"
1111
- For i.MX8MM SoCs should be "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"
12+
- For i.MX8MN SoCs should be "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"
13+
- For i.MX8MP SoCs should be "fsl,imx8mp-src", "syscon"
1214
- reg: should be register base and length as documented in the
1315
datasheet
1416
- interrupts: Should contain SRC interrupt
@@ -49,4 +51,6 @@ Example:
4951
For list of all valid reset indices see
5052
<dt-bindings/reset/imx7-reset.h> for i.MX7,
5153
<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ and
52-
<dt-bindings/reset/imx8mq-reset.h> for i.MX8MM
54+
<dt-bindings/reset/imx8mq-reset.h> for i.MX8MM and
55+
<dt-bindings/reset/imx8mq-reset.h> for i.MX8MN and
56+
<dt-bindings/reset/imx8mp-reset.h> for i.MX8MP

‎drivers/reset/hisilicon/hi6220_reset.c

Lines changed: 68 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@
3333
enum hi6220_reset_ctrl_type {
3434
PERIPHERAL,
3535
MEDIA,
36+
AO,
3637
};
3738

3839
struct hi6220_reset_data {
@@ -92,6 +93,65 @@ static const struct reset_control_ops hi6220_media_reset_ops = {
9293
.deassert = hi6220_media_deassert,
9394
};
9495

96+
#define AO_SCTRL_SC_PW_CLKEN0 0x800
97+
#define AO_SCTRL_SC_PW_CLKDIS0 0x804
98+
99+
#define AO_SCTRL_SC_PW_RSTEN0 0x810
100+
#define AO_SCTRL_SC_PW_RSTDIS0 0x814
101+
102+
#define AO_SCTRL_SC_PW_ISOEN0 0x820
103+
#define AO_SCTRL_SC_PW_ISODIS0 0x824
104+
#define AO_MAX_INDEX 12
105+
106+
static int hi6220_ao_assert(struct reset_controller_dev *rc_dev,
107+
unsigned long idx)
108+
{
109+
struct hi6220_reset_data *data = to_reset_data(rc_dev);
110+
struct regmap *regmap = data->regmap;
111+
int ret;
112+
113+
ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTEN0, BIT(idx));
114+
if (ret)
115+
return ret;
116+
117+
ret = regmap_write(regmap, AO_SCTRL_SC_PW_ISOEN0, BIT(idx));
118+
if (ret)
119+
return ret;
120+
121+
ret = regmap_write(regmap, AO_SCTRL_SC_PW_CLKDIS0, BIT(idx));
122+
return ret;
123+
}
124+
125+
static int hi6220_ao_deassert(struct reset_controller_dev *rc_dev,
126+
unsigned long idx)
127+
{
128+
struct hi6220_reset_data *data = to_reset_data(rc_dev);
129+
struct regmap *regmap = data->regmap;
130+
int ret;
131+
132+
/*
133+
* It was suggested to disable isolation before enabling
134+
* the clocks and deasserting reset, to avoid glitches.
135+
* But this order is preserved to keep it matching the
136+
* vendor code.
137+
*/
138+
ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTDIS0, BIT(idx));
139+
if (ret)
140+
return ret;
141+
142+
ret = regmap_write(regmap, AO_SCTRL_SC_PW_ISODIS0, BIT(idx));
143+
if (ret)
144+
return ret;
145+
146+
ret = regmap_write(regmap, AO_SCTRL_SC_PW_CLKEN0, BIT(idx));
147+
return ret;
148+
}
149+
150+
static const struct reset_control_ops hi6220_ao_reset_ops = {
151+
.assert = hi6220_ao_assert,
152+
.deassert = hi6220_ao_deassert,
153+
};
154+
95155
static int hi6220_reset_probe(struct platform_device *pdev)
96156
{
97157
struct device_node *np = pdev->dev.of_node;
@@ -117,9 +177,12 @@ static int hi6220_reset_probe(struct platform_device *pdev)
117177
if (type == MEDIA) {
118178
data->rc_dev.ops = &hi6220_media_reset_ops;
119179
data->rc_dev.nr_resets = MEDIA_MAX_INDEX;
120-
} else {
180+
} else if (type == PERIPHERAL) {
121181
data->rc_dev.ops = &hi6220_peripheral_reset_ops;
122182
data->rc_dev.nr_resets = PERIPH_MAX_INDEX;
183+
} else {
184+
data->rc_dev.ops = &hi6220_ao_reset_ops;
185+
data->rc_dev.nr_resets = AO_MAX_INDEX;
123186
}
124187

125188
return reset_controller_register(&data->rc_dev);
@@ -134,6 +197,10 @@ static const struct of_device_id hi6220_reset_match[] = {
134197
.compatible = "hisilicon,hi6220-mediactrl",
135198
.data = (void *)MEDIA,
136199
},
200+
{
201+
.compatible = "hisilicon,hi6220-aoctrl",
202+
.data = (void *)AO,
203+
},
137204
{ /* sentinel */ },
138205
};
139206
MODULE_DEVICE_TABLE(of, hi6220_reset_match);

‎drivers/reset/reset-imx7.c

Lines changed: 101 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include <linux/regmap.h>
1616
#include <dt-bindings/reset/imx7-reset.h>
1717
#include <dt-bindings/reset/imx8mq-reset.h>
18+
#include <dt-bindings/reset/imx8mp-reset.h>
1819

1920
struct imx7_src_signal {
2021
unsigned int offset, bit;
@@ -145,6 +146,18 @@ enum imx8mq_src_registers {
145146
SRC_DDRC2_RCR = 0x1004,
146147
};
147148

149+
enum imx8mp_src_registers {
150+
SRC_SUPERMIX_RCR = 0x0018,
151+
SRC_AUDIOMIX_RCR = 0x001c,
152+
SRC_MLMIX_RCR = 0x0028,
153+
SRC_GPU2D_RCR = 0x0038,
154+
SRC_GPU3D_RCR = 0x003c,
155+
SRC_VPU_G1_RCR = 0x0048,
156+
SRC_VPU_G2_RCR = 0x004c,
157+
SRC_VPUVC8KE_RCR = 0x0050,
158+
SRC_NOC_RCR = 0x0054,
159+
};
160+
148161
static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
149162
[IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
150163
[IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
@@ -253,6 +266,93 @@ static const struct imx7_src_variant variant_imx8mq = {
253266
},
254267
};
255268

269+
static const struct imx7_src_signal imx8mp_src_signals[IMX8MP_RESET_NUM] = {
270+
[IMX8MP_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
271+
[IMX8MP_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
272+
[IMX8MP_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
273+
[IMX8MP_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
274+
[IMX8MP_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
275+
[IMX8MP_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
276+
[IMX8MP_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
277+
[IMX8MP_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
278+
[IMX8MP_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
279+
[IMX8MP_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
280+
[IMX8MP_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
281+
[IMX8MP_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
282+
[IMX8MP_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
283+
[IMX8MP_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
284+
[IMX8MP_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
285+
[IMX8MP_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
286+
[IMX8MP_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
287+
[IMX8MP_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
288+
[IMX8MP_RESET_SW_NON_SCLR_M7C_RST] = { SRC_M4RCR, BIT(0) },
289+
[IMX8MP_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
290+
[IMX8MP_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
291+
[IMX8MP_RESET_SUPERMIX_RESET] = { SRC_SUPERMIX_RCR, BIT(0) },
292+
[IMX8MP_RESET_AUDIOMIX_RESET] = { SRC_AUDIOMIX_RCR, BIT(0) },
293+
[IMX8MP_RESET_MLMIX_RESET] = { SRC_MLMIX_RCR, BIT(0) },
294+
[IMX8MP_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) },
295+
[IMX8MP_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
296+
[IMX8MP_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
297+
[IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
298+
[IMX8MP_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
299+
[IMX8MP_RESET_MEDIA_RESET] = { SRC_DISP_RCR, BIT(0) },
300+
[IMX8MP_RESET_GPU2D_RESET] = { SRC_GPU2D_RCR, BIT(0) },
301+
[IMX8MP_RESET_GPU3D_RESET] = { SRC_GPU3D_RCR, BIT(0) },
302+
[IMX8MP_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
303+
[IMX8MP_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
304+
[IMX8MP_RESET_VPU_G1_RESET] = { SRC_VPU_G1_RCR, BIT(0) },
305+
[IMX8MP_RESET_VPU_G2_RESET] = { SRC_VPU_G2_RCR, BIT(0) },
306+
[IMX8MP_RESET_VPUVC8KE_RESET] = { SRC_VPUVC8KE_RCR, BIT(0) },
307+
[IMX8MP_RESET_NOC_RESET] = { SRC_NOC_RCR, BIT(0) },
308+
};
309+
310+
static int imx8mp_reset_set(struct reset_controller_dev *rcdev,
311+
unsigned long id, bool assert)
312+
{
313+
struct imx7_src *imx7src = to_imx7_src(rcdev);
314+
const unsigned int bit = imx7src->signals[id].bit;
315+
unsigned int value = assert ? bit : 0;
316+
317+
switch (id) {
318+
case IMX8MP_RESET_PCIEPHY:
319+
/*
320+
* wait for more than 10us to release phy g_rst and
321+
* btnrst
322+
*/
323+
if (!assert)
324+
udelay(10);
325+
break;
326+
327+
case IMX8MP_RESET_PCIE_CTRL_APPS_EN:
328+
value = assert ? 0 : bit;
329+
break;
330+
}
331+
332+
return imx7_reset_update(imx7src, id, value);
333+
}
334+
335+
static int imx8mp_reset_assert(struct reset_controller_dev *rcdev,
336+
unsigned long id)
337+
{
338+
return imx8mp_reset_set(rcdev, id, true);
339+
}
340+
341+
static int imx8mp_reset_deassert(struct reset_controller_dev *rcdev,
342+
unsigned long id)
343+
{
344+
return imx8mp_reset_set(rcdev, id, false);
345+
}
346+
347+
static const struct imx7_src_variant variant_imx8mp = {
348+
.signals = imx8mp_src_signals,
349+
.signals_num = ARRAY_SIZE(imx8mp_src_signals),
350+
.ops = {
351+
.assert = imx8mp_reset_assert,
352+
.deassert = imx8mp_reset_deassert,
353+
},
354+
};
355+
256356
static int imx7_reset_probe(struct platform_device *pdev)
257357
{
258358
struct imx7_src *imx7src;
@@ -283,6 +383,7 @@ static int imx7_reset_probe(struct platform_device *pdev)
283383
static const struct of_device_id imx7_reset_dt_ids[] = {
284384
{ .compatible = "fsl,imx7d-src", .data = &variant_imx7 },
285385
{ .compatible = "fsl,imx8mq-src", .data = &variant_imx8mq },
386+
{ .compatible = "fsl,imx8mp-src", .data = &variant_imx8mp },
286387
{ /* sentinel */ },
287388
};
288389

‎include/dt-bindings/reset/amlogic,meson-gxbb-reset.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@
6969
#define RESET_SYS_CPU_L2 58
7070
#define RESET_SYS_CPU_P 59
7171
#define RESET_SYS_CPU_MBIST 60
72-
/* 61 */
72+
#define RESET_ACODEC 61
7373
/* 62 */
7474
/* 63 */
7575
/* RESET2 */

‎include/dt-bindings/reset/imx8mp-reset.h

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,50 @@
1+
/* SPDX-License-Identifier: GPL-2.0-only */
2+
/*
3+
* Copyright 2020 NXP
4+
*/
5+
6+
#ifndef DT_BINDING_RESET_IMX8MP_H
7+
#define DT_BINDING_RESET_IMX8MP_H
8+
9+
#define IMX8MP_RESET_A53_CORE_POR_RESET0 0
10+
#define IMX8MP_RESET_A53_CORE_POR_RESET1 1
11+
#define IMX8MP_RESET_A53_CORE_POR_RESET2 2
12+
#define IMX8MP_RESET_A53_CORE_POR_RESET3 3
13+
#define IMX8MP_RESET_A53_CORE_RESET0 4
14+
#define IMX8MP_RESET_A53_CORE_RESET1 5
15+
#define IMX8MP_RESET_A53_CORE_RESET2 6
16+
#define IMX8MP_RESET_A53_CORE_RESET3 7
17+
#define IMX8MP_RESET_A53_DBG_RESET0 8
18+
#define IMX8MP_RESET_A53_DBG_RESET1 9
19+
#define IMX8MP_RESET_A53_DBG_RESET2 10
20+
#define IMX8MP_RESET_A53_DBG_RESET3 11
21+
#define IMX8MP_RESET_A53_ETM_RESET0 12
22+
#define IMX8MP_RESET_A53_ETM_RESET1 13
23+
#define IMX8MP_RESET_A53_ETM_RESET2 14
24+
#define IMX8MP_RESET_A53_ETM_RESET3 15
25+
#define IMX8MP_RESET_A53_SOC_DBG_RESET 16
26+
#define IMX8MP_RESET_A53_L2RESET 17
27+
#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST 18
28+
#define IMX8MP_RESET_OTG1_PHY_RESET 19
29+
#define IMX8MP_RESET_OTG2_PHY_RESET 20
30+
#define IMX8MP_RESET_SUPERMIX_RESET 21
31+
#define IMX8MP_RESET_AUDIOMIX_RESET 22
32+
#define IMX8MP_RESET_MLMIX_RESET 23
33+
#define IMX8MP_RESET_PCIEPHY 24
34+
#define IMX8MP_RESET_PCIEPHY_PERST 25
35+
#define IMX8MP_RESET_PCIE_CTRL_APPS_EN 26
36+
#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF 27
37+
#define IMX8MP_RESET_HDMI_PHY_APB_RESET 28
38+
#define IMX8MP_RESET_MEDIA_RESET 29
39+
#define IMX8MP_RESET_GPU2D_RESET 30
40+
#define IMX8MP_RESET_GPU3D_RESET 31
41+
#define IMX8MP_RESET_GPU_RESET 32
42+
#define IMX8MP_RESET_VPU_RESET 33
43+
#define IMX8MP_RESET_VPU_G1_RESET 34
44+
#define IMX8MP_RESET_VPU_G2_RESET 35
45+
#define IMX8MP_RESET_VPUVC8KE_RESET 36
46+
#define IMX8MP_RESET_NOC_RESET 37
47+
48+
#define IMX8MP_RESET_NUM 38
49+
50+
#endif

‎include/dt-bindings/reset/imx8mq-reset.h

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -28,36 +28,36 @@
2828
#define IMX8MQ_RESET_A53_L2RESET 17
2929
#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18
3030
#define IMX8MQ_RESET_OTG1_PHY_RESET 19
31-
#define IMX8MQ_RESET_OTG2_PHY_RESET 20
32-
#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21
33-
#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22
34-
#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23
35-
#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24
36-
#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25
37-
#define IMX8MQ_RESET_PCIEPHY 26
38-
#define IMX8MQ_RESET_PCIEPHY_PERST 27
39-
#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28
40-
#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29
41-
#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM does NOT support */
31+
#define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */
32+
#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */
33+
#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */
34+
#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */
35+
#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */
36+
#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */
37+
#define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */
38+
#define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */
39+
#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */
40+
#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */
41+
#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM/i.MX8MN does NOT support */
4242
#define IMX8MQ_RESET_DISP_RESET 31
4343
#define IMX8MQ_RESET_GPU_RESET 32
44-
#define IMX8MQ_RESET_VPU_RESET 33
45-
#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM does NOT support */
46-
#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM does NOT support */
47-
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM does NOT support */
48-
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM does NOT support */
49-
#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM does NOT support */
50-
#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM does NOT support */
51-
#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM does NOT support */
52-
#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM does NOT support */
53-
#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM does NOT support */
54-
#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM does NOT support */
55-
#define IMX8MQ_RESET_DDRC1_PRST 44
56-
#define IMX8MQ_RESET_DDRC1_CORE_RESET 45
57-
#define IMX8MQ_RESET_DDRC1_PHY_RESET 46
58-
#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM does NOT support */
59-
#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM does NOT support */
60-
#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM does NOT support */
44+
#define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT support */
45+
#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does NOT support */
46+
#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */
47+
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */
48+
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */
49+
#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */
50+
#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */
51+
#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */
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#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */
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#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */
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#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */
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#define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does NOT support */
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#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT support */
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#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT support */
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#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM/i.MX8MN does NOT support */
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#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does NOT support */
60+
#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does NOT support */
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#define IMX8MQ_RESET_NUM 50
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