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parakatsbogend
paraka
authored and
tsbogend
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mips: ralink: mt7620: remove clock related code
A proper clock driver for ralink SoCs has been added. Hence there is no need to have clock related code in 'arch/mips/ralink' folder anymore. Since this is the last clock related code removal, remove also remaining prototypes in 'common.h' header file. Signed-off-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
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‎arch/mips/include/asm/mach-ralink/mt7620.h

Lines changed: 0 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -20,52 +20,17 @@
2020
#define SYSC_REG_CHIP_REV 0x0c
2121
#define SYSC_REG_SYSTEM_CONFIG0 0x10
2222
#define SYSC_REG_SYSTEM_CONFIG1 0x14
23-
#define SYSC_REG_CLKCFG0 0x2c
24-
#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
25-
#define SYSC_REG_CPLL_CONFIG0 0x54
26-
#define SYSC_REG_CPLL_CONFIG1 0x58
2723

2824
#define MT7620_CHIP_NAME0 0x3637544d
2925
#define MT7620_CHIP_NAME1 0x20203032
3026
#define MT7628_CHIP_NAME1 0x20203832
3127

32-
#define SYSCFG0_XTAL_FREQ_SEL BIT(6)
33-
3428
#define CHIP_REV_PKG_MASK 0x1
3529
#define CHIP_REV_PKG_SHIFT 16
3630
#define CHIP_REV_VER_MASK 0xf
3731
#define CHIP_REV_VER_SHIFT 8
3832
#define CHIP_REV_ECO_MASK 0xf
3933

40-
#define CLKCFG0_PERI_CLK_SEL BIT(4)
41-
42-
#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
43-
#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
44-
#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
45-
#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
46-
#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
47-
#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
48-
#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
49-
#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
50-
#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
51-
#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
52-
#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
53-
#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
54-
#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
55-
#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
56-
#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
57-
58-
#define CPLL_CFG0_SW_CFG BIT(31)
59-
#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
60-
#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
61-
#define CPLL_CFG0_LC_CURFCK BIT(15)
62-
#define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
63-
#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
64-
#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
65-
66-
#define CPLL_CFG1_CPU_AUX1 BIT(25)
67-
#define CPLL_CFG1_CPU_AUX0 BIT(24)
68-
6934
#define SYSCFG0_DRAM_TYPE_MASK 0x3
7035
#define SYSCFG0_DRAM_TYPE_SHIFT 4
7136
#define SYSCFG0_DRAM_TYPE_SDRAM 0

‎arch/mips/ralink/common.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -23,9 +23,6 @@ extern struct ralink_soc_info soc_info;
2323

2424
extern void ralink_of_remap(void);
2525

26-
extern void ralink_clk_init(void);
27-
extern void ralink_clk_add(const char *dev, unsigned long rate);
28-
2926
extern void ralink_rst_init(void);
3027

3128
extern void __init prom_soc_init(struct ralink_soc_info *soc_info);

‎arch/mips/ralink/mt7620.c

Lines changed: 0 additions & 226 deletions
Original file line numberDiff line numberDiff line change
@@ -36,12 +36,6 @@
3636
#define PMU1_CFG 0x8C
3737
#define DIG_SW_SEL BIT(25)
3838

39-
/* clock scaling */
40-
#define CLKCFG_FDIV_MASK 0x1f00
41-
#define CLKCFG_FDIV_USB_VAL 0x0300
42-
#define CLKCFG_FFRAC_MASK 0x001f
43-
#define CLKCFG_FFRAC_USB_VAL 0x0003
44-
4539
/* EFUSE bits */
4640
#define EFUSE_MT7688 0x100000
4741

@@ -53,226 +47,6 @@ static int dram_type;
5347

5448
static struct ralink_soc_info *soc_info_ptr;
5549

56-
static __init u32
57-
mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
58-
{
59-
u64 t;
60-
61-
t = ref_rate;
62-
t *= mul;
63-
do_div(t, div);
64-
65-
return t;
66-
}
67-
68-
#define MHZ(x) ((x) * 1000 * 1000)
69-
70-
static __init unsigned long
71-
mt7620_get_xtal_rate(void)
72-
{
73-
u32 reg;
74-
75-
reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
76-
if (reg & SYSCFG0_XTAL_FREQ_SEL)
77-
return MHZ(40);
78-
79-
return MHZ(20);
80-
}
81-
82-
static __init unsigned long
83-
mt7620_get_periph_rate(unsigned long xtal_rate)
84-
{
85-
u32 reg;
86-
87-
reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
88-
if (reg & CLKCFG0_PERI_CLK_SEL)
89-
return xtal_rate;
90-
91-
return MHZ(40);
92-
}
93-
94-
static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
95-
96-
static __init unsigned long
97-
mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
98-
{
99-
u32 reg;
100-
u32 mul;
101-
u32 div;
102-
103-
reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
104-
if (reg & CPLL_CFG0_BYPASS_REF_CLK)
105-
return xtal_rate;
106-
107-
if ((reg & CPLL_CFG0_SW_CFG) == 0)
108-
return MHZ(600);
109-
110-
mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
111-
CPLL_CFG0_PLL_MULT_RATIO_MASK;
112-
mul += 24;
113-
if (reg & CPLL_CFG0_LC_CURFCK)
114-
mul *= 2;
115-
116-
div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
117-
CPLL_CFG0_PLL_DIV_RATIO_MASK;
118-
119-
WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
120-
121-
return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
122-
}
123-
124-
static __init unsigned long
125-
mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
126-
{
127-
u32 reg;
128-
129-
reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
130-
if (reg & CPLL_CFG1_CPU_AUX1)
131-
return xtal_rate;
132-
133-
if (reg & CPLL_CFG1_CPU_AUX0)
134-
return MHZ(480);
135-
136-
return cpu_pll_rate;
137-
}
138-
139-
static __init unsigned long
140-
mt7620_get_cpu_rate(unsigned long pll_rate)
141-
{
142-
u32 reg;
143-
u32 mul;
144-
u32 div;
145-
146-
reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
147-
148-
mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
149-
div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
150-
CPU_SYS_CLKCFG_CPU_FDIV_MASK;
151-
152-
return mt7620_calc_rate(pll_rate, mul, div);
153-
}
154-
155-
static const u32 mt7620_ocp_dividers[16] __initconst = {
156-
[CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
157-
[CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
158-
[CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
159-
[CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
160-
[CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
161-
};
162-
163-
static __init unsigned long
164-
mt7620_get_dram_rate(unsigned long pll_rate)
165-
{
166-
if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
167-
return pll_rate / 4;
168-
169-
return pll_rate / 3;
170-
}
171-
172-
static __init unsigned long
173-
mt7620_get_sys_rate(unsigned long cpu_rate)
174-
{
175-
u32 reg;
176-
u32 ocp_ratio;
177-
u32 div;
178-
179-
reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
180-
181-
ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
182-
CPU_SYS_CLKCFG_OCP_RATIO_MASK;
183-
184-
if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
185-
return cpu_rate;
186-
187-
div = mt7620_ocp_dividers[ocp_ratio];
188-
if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
189-
return cpu_rate;
190-
191-
return cpu_rate / div;
192-
}
193-
194-
void __init ralink_clk_init(void)
195-
{
196-
unsigned long xtal_rate;
197-
unsigned long cpu_pll_rate;
198-
unsigned long pll_rate;
199-
unsigned long cpu_rate;
200-
unsigned long sys_rate;
201-
unsigned long dram_rate;
202-
unsigned long periph_rate;
203-
unsigned long pcmi2s_rate;
204-
205-
xtal_rate = mt7620_get_xtal_rate();
206-
207-
#define RFMT(label) label ":%lu.%03luMHz "
208-
#define RINT(x) ((x) / 1000000)
209-
#define RFRAC(x) (((x) / 1000) % 1000)
210-
211-
if (is_mt76x8()) {
212-
if (xtal_rate == MHZ(40))
213-
cpu_rate = MHZ(580);
214-
else
215-
cpu_rate = MHZ(575);
216-
dram_rate = sys_rate = cpu_rate / 3;
217-
periph_rate = MHZ(40);
218-
pcmi2s_rate = MHZ(480);
219-
220-
ralink_clk_add("10000d00.uartlite", periph_rate);
221-
ralink_clk_add("10000e00.uartlite", periph_rate);
222-
} else {
223-
cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
224-
pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
225-
226-
cpu_rate = mt7620_get_cpu_rate(pll_rate);
227-
dram_rate = mt7620_get_dram_rate(pll_rate);
228-
sys_rate = mt7620_get_sys_rate(cpu_rate);
229-
periph_rate = mt7620_get_periph_rate(xtal_rate);
230-
pcmi2s_rate = periph_rate;
231-
232-
pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
233-
RINT(xtal_rate), RFRAC(xtal_rate),
234-
RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
235-
RINT(pll_rate), RFRAC(pll_rate));
236-
237-
ralink_clk_add("10000500.uart", periph_rate);
238-
}
239-
240-
pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
241-
RINT(cpu_rate), RFRAC(cpu_rate),
242-
RINT(dram_rate), RFRAC(dram_rate),
243-
RINT(sys_rate), RFRAC(sys_rate),
244-
RINT(periph_rate), RFRAC(periph_rate));
245-
#undef RFRAC
246-
#undef RINT
247-
#undef RFMT
248-
249-
ralink_clk_add("cpu", cpu_rate);
250-
ralink_clk_add("10000100.timer", periph_rate);
251-
ralink_clk_add("10000120.watchdog", periph_rate);
252-
ralink_clk_add("10000900.i2c", periph_rate);
253-
ralink_clk_add("10000a00.i2s", pcmi2s_rate);
254-
ralink_clk_add("10000b00.spi", sys_rate);
255-
ralink_clk_add("10000b40.spi", sys_rate);
256-
ralink_clk_add("10000c00.uartlite", periph_rate);
257-
ralink_clk_add("10000d00.uart1", periph_rate);
258-
ralink_clk_add("10000e00.uart2", periph_rate);
259-
ralink_clk_add("10180000.wmac", xtal_rate);
260-
261-
if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
262-
/*
263-
* When the CPU goes into sleep mode, the BUS clock will be
264-
* too low for USB to function properly. Adjust the busses
265-
* fractional divider to fix this
266-
*/
267-
u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
268-
269-
val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
270-
val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
271-
272-
rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
273-
}
274-
}
275-
27650
void __init ralink_of_remap(void)
27751
{
27852
rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");

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