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Xiaojie Yuanalexdeucher
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drm/amdgpu/sdma5: fix wptr overwritten in ->get_wptr()
"u64 *wptr" points to the the wptr value in write back buffer and "*wptr = (*wptr) >> 2;" results in the value being overwritten each time when ->get_wptr() is called. umr uses /sys/kernel/debug/dri/0/amdgpu_ring_sdma0 to get rptr/wptr and decode ring content and it is affected by this issue. fix and simplify the logic similar as sdma_v4_0_ring_get_wptr(). v2: fix for sdma5.2 as well v3: drop sdma 5.2 changes for 5.8 and stable Suggested-by: Le Ma <[email protected]> Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
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drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

Lines changed: 8 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -314,30 +314,20 @@ static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
314314
static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
315315
{
316316
struct amdgpu_device *adev = ring->adev;
317-
u64 *wptr = NULL;
318-
uint64_t local_wptr = 0;
317+
u64 wptr;
319318

320319
if (ring->use_doorbell) {
321320
/* XXX check if swapping is necessary on BE */
322-
wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]);
323-
DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr);
324-
*wptr = (*wptr) >> 2;
325-
DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr);
321+
wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
322+
DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
326323
} else {
327-
u32 lowbit, highbit;
328-
329-
wptr = &local_wptr;
330-
lowbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
331-
highbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
332-
333-
DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
334-
ring->me, highbit, lowbit);
335-
*wptr = highbit;
336-
*wptr = (*wptr) << 32;
337-
*wptr |= lowbit;
324+
wptr = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
325+
wptr = wptr << 32;
326+
wptr |= RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
327+
DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
338328
}
339329

340-
return *wptr;
330+
return wptr >> 2;
341331
}
342332

343333
/**

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