Skip to content

Commit 0607a50

Browse files
tobiasjakobialexdeucher
authored andcommitted
drm/amd/display: Avoid race between dcn35_set_drr() and dc_state_destruct()
dc_state_destruct() nulls the resource context of the DC state. The pipe context passed to dcn35_set_drr() is a member of this resource context. If dc_state_destruct() is called parallel to the IRQ processing (which calls dcn35_set_drr() at some point), we can end up using already nulled function callback fields of struct stream_resource. The logic in dcn35_set_drr() already tries to avoid this, by checking tg against NULL. But if the nulling happens exactly after the NULL check and before the next access, then we get a race. Avoid this by copying tg first to a local variable, and then use this variable for all the operations. This should work, as long as nobody frees the resource pool where the timing generators live. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3142 Fixes: 06ad7e1 ("drm/amd/display: Destroy DC context while keeping DML and DML2") Signed-off-by: Tobias Jakobi <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
1 parent a3cc326 commit 0607a50

File tree

1 file changed

+12
-8
lines changed

1 file changed

+12
-8
lines changed

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

Lines changed: 12 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1414,7 +1414,13 @@ void dcn35_set_drr(struct pipe_ctx **pipe_ctx,
14141414
params.vertical_total_mid_frame_num = adjust.v_total_mid_frame_num;
14151415

14161416
for (i = 0; i < num_pipes; i++) {
1417-
if ((pipe_ctx[i]->stream_res.tg != NULL) && pipe_ctx[i]->stream_res.tg->funcs) {
1417+
/* dc_state_destruct() might null the stream resources, so fetch tg
1418+
* here first to avoid a race condition. The lifetime of the pointee
1419+
* itself (the timing_generator object) is not a problem here.
1420+
*/
1421+
struct timing_generator *tg = pipe_ctx[i]->stream_res.tg;
1422+
1423+
if ((tg != NULL) && tg->funcs) {
14181424
if (pipe_ctx[i]->stream && pipe_ctx[i]->stream->ctx->dc->debug.static_screen_wait_frames) {
14191425
struct dc_crtc_timing *timing = &pipe_ctx[i]->stream->timing;
14201426
struct dc *dc = pipe_ctx[i]->stream->ctx->dc;
@@ -1426,14 +1432,12 @@ void dcn35_set_drr(struct pipe_ctx **pipe_ctx,
14261432
num_frames = 2 * (frame_rate % 60);
14271433
}
14281434
}
1429-
if (pipe_ctx[i]->stream_res.tg->funcs->set_drr)
1430-
pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1431-
pipe_ctx[i]->stream_res.tg, &params);
1435+
if (tg->funcs->set_drr)
1436+
tg->funcs->set_drr(tg, &params);
14321437
if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
1433-
if (pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control)
1434-
pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1435-
pipe_ctx[i]->stream_res.tg,
1436-
event_triggers, num_frames);
1438+
if (tg->funcs->set_static_screen_control)
1439+
tg->funcs->set_static_screen_control(
1440+
tg, event_triggers, num_frames);
14371441
}
14381442
}
14391443
}

0 commit comments

Comments
 (0)