Skip to content

Commit 06097b1

Browse files
lumaglumag
committed
dt-bindings: display/msm: split dpu-qcm2290 into DPU and MDSS parts
In order to make the schema more readable, split dpu-qcm2290 into the DPU and MDSS parts, each one describing just a single device binding. Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/508383/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
1 parent 9410872 commit 06097b1

File tree

3 files changed

+201
-148
lines changed

3 files changed

+201
-148
lines changed

‎Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml

Lines changed: 0 additions & 148 deletions
This file was deleted.

‎Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml

Lines changed: 84 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,84 @@
1+
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-dpu.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Qualcomm Display DPU dt properties for QCM2290 target
8+
9+
maintainers:
10+
- Loic Poulain <[email protected]>
11+
12+
$ref: /schemas/display/msm/dpu-common.yaml#
13+
14+
properties:
15+
compatible:
16+
items:
17+
- const: qcom,qcm2290-dpu
18+
19+
reg:
20+
items:
21+
- description: Address offset and size for mdp register set
22+
- description: Address offset and size for vbif register set
23+
24+
reg-names:
25+
items:
26+
- const: mdp
27+
- const: vbif
28+
29+
clocks:
30+
items:
31+
- description: Display AXI clock from gcc
32+
- description: Display AHB clock from dispcc
33+
- description: Display core clock from dispcc
34+
- description: Display lut clock from dispcc
35+
- description: Display vsync clock from dispcc
36+
37+
clock-names:
38+
items:
39+
- const: bus
40+
- const: iface
41+
- const: core
42+
- const: lut
43+
- const: vsync
44+
45+
unevaluatedProperties: false
46+
47+
examples:
48+
- |
49+
#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
50+
#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
51+
#include <dt-bindings/power/qcom-rpmpd.h>
52+
53+
display-controller@5e01000 {
54+
compatible = "qcom,qcm2290-dpu";
55+
reg = <0x05e01000 0x8f000>,
56+
<0x05eb0000 0x2008>;
57+
reg-names = "mdp", "vbif";
58+
59+
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
60+
<&dispcc DISP_CC_MDSS_AHB_CLK>,
61+
<&dispcc DISP_CC_MDSS_MDP_CLK>,
62+
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
63+
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
64+
clock-names = "bus", "iface", "core", "lut", "vsync";
65+
66+
operating-points-v2 = <&mdp_opp_table>;
67+
power-domains = <&rpmpd QCM2290_VDDCX>;
68+
69+
interrupt-parent = <&mdss>;
70+
interrupts = <0>;
71+
72+
ports {
73+
#address-cells = <1>;
74+
#size-cells = <0>;
75+
76+
port@0 {
77+
reg = <0>;
78+
endpoint {
79+
remote-endpoint = <&dsi0_in>;
80+
};
81+
};
82+
};
83+
};
84+
...

‎Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml

Lines changed: 117 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,117 @@
1+
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Qualcomm QCM220 Display MDSS
8+
9+
maintainers:
10+
- Loic Poulain <[email protected]>
11+
12+
description:
13+
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14+
sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
15+
are mentioned for QCM2290 target.
16+
17+
$ref: /schemas/display/msm/mdss-common.yaml#
18+
19+
properties:
20+
compatible:
21+
items:
22+
- const: qcom,qcm2290-mdss
23+
24+
clocks:
25+
items:
26+
- description: Display AHB clock from gcc
27+
- description: Display AXI clock
28+
- description: Display core clock
29+
30+
clock-names:
31+
items:
32+
- const: iface
33+
- const: bus
34+
- const: core
35+
36+
iommus:
37+
maxItems: 2
38+
39+
interconnects:
40+
maxItems: 1
41+
42+
interconnect-names:
43+
maxItems: 1
44+
45+
patternProperties:
46+
"^display-controller@[0-9a-f]+$":
47+
type: object
48+
properties:
49+
compatible:
50+
const: qcom,qcm2290-dpu
51+
52+
unevaluatedProperties: false
53+
54+
examples:
55+
- |
56+
#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
57+
#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
58+
#include <dt-bindings/interrupt-controller/arm-gic.h>
59+
#include <dt-bindings/interconnect/qcom,qcm2290.h>
60+
#include <dt-bindings/power/qcom-rpmpd.h>
61+
62+
mdss@5e00000 {
63+
#address-cells = <1>;
64+
#size-cells = <1>;
65+
compatible = "qcom,qcm2290-mdss";
66+
reg = <0x05e00000 0x1000>;
67+
reg-names = "mdss";
68+
power-domains = <&dispcc MDSS_GDSC>;
69+
clocks = <&gcc GCC_DISP_AHB_CLK>,
70+
<&gcc GCC_DISP_HF_AXI_CLK>,
71+
<&dispcc DISP_CC_MDSS_MDP_CLK>;
72+
clock-names = "iface", "bus", "core";
73+
74+
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
75+
interrupt-controller;
76+
#interrupt-cells = <1>;
77+
78+
interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>;
79+
interconnect-names = "mdp0-mem";
80+
81+
iommus = <&apps_smmu 0x420 0x2>,
82+
<&apps_smmu 0x421 0x0>;
83+
ranges;
84+
85+
display-controller@5e01000 {
86+
compatible = "qcom,qcm2290-dpu";
87+
reg = <0x05e01000 0x8f000>,
88+
<0x05eb0000 0x2008>;
89+
reg-names = "mdp", "vbif";
90+
91+
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
92+
<&dispcc DISP_CC_MDSS_AHB_CLK>,
93+
<&dispcc DISP_CC_MDSS_MDP_CLK>,
94+
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
95+
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
96+
clock-names = "bus", "iface", "core", "lut", "vsync";
97+
98+
operating-points-v2 = <&mdp_opp_table>;
99+
power-domains = <&rpmpd QCM2290_VDDCX>;
100+
101+
interrupt-parent = <&mdss>;
102+
interrupts = <0>;
103+
104+
ports {
105+
#address-cells = <1>;
106+
#size-cells = <0>;
107+
108+
port@0 {
109+
reg = <0>;
110+
dpu_intf1_out: endpoint {
111+
remote-endpoint = <&dsi0_in>;
112+
};
113+
};
114+
};
115+
};
116+
};
117+
...

0 commit comments

Comments
 (0)