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#define REG_MMU_INVLD_START_A 0x024
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#define REG_MMU_INVLD_END_A 0x028
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+ #define REG_MMU_INV_SEL_GEN2 0x02c
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#define REG_MMU_INV_SEL_GEN1 0x038
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#define F_INVLD_EN0 BIT(0)
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#define F_INVLD_EN1 BIT(1)
@@ -808,6 +809,13 @@ static const struct mtk_iommu_plat_data mt2712_data = {
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.larbid_remap = {{0 }, {1 }, {2 }, {3 }, {4 }, {5 }, {6 }, {7 }},
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};
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+ static const struct mtk_iommu_plat_data mt6779_data = {
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+ .m4u_plat = M4U_MT6779 ,
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+ .flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN ,
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+ .inv_sel_reg = REG_MMU_INV_SEL_GEN2 ,
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+ .larbid_remap = {{0 }, {1 }, {2 }, {3 }, {5 }, {7 , 8 }, {10 }, {9 }},
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+ };
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+
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static const struct mtk_iommu_plat_data mt8173_data = {
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.m4u_plat = M4U_MT8173 ,
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.flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI ,
@@ -824,6 +832,7 @@ static const struct mtk_iommu_plat_data mt8183_data = {
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static const struct of_device_id mtk_iommu_of_ids [] = {
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{ .compatible = "mediatek,mt2712-m4u" , .data = & mt2712_data },
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+ { .compatible = "mediatek,mt6779-m4u" , .data = & mt6779_data },
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{ .compatible = "mediatek,mt8173-m4u" , .data = & mt8173_data },
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{ .compatible = "mediatek,mt8183-m4u" , .data = & mt8183_data },
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{}
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