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Merge tag 'arm-soc/for-6.0/devicetree' of https://github.com/Broadcom/stblinux into arm/fixes
This pull request contains Broadcom ARM-based SoCs Device Tree fixes for 6.0, please pull the following: - William fixes a number of the recently submitted DTS files for 63178, 6846, 6878 to have correct PSCI node propertie as well as correct timer CPU masks * tag 'arm-soc/for-6.0/devicetree' of https://github.com/Broadcom/stblinux: ARM: dts: bcmbca: bcm6878: cosmetic change ARM: dts: bcmbca: bcm6878: fix timer node cpu mask flag ARM: dts: bcmbca: bcm6846: fix interrupt controller node ARM: dts: bcmbca: bcm6846: clean up psci node ARM: dts: bcmbca: bcm6846: fix timer node cpu mask flag ARM: dts: bcmbca: bcm63178: cosmetic change ARM: dts: bcmbca: bcm63178: fix interrupt controller node ARM: dts: bcmbca: bcm63178: clean up psci node ARM: dts: bcmbca: bcm63178: fix timer node cpu mask flag Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2 parents 92c7c5b + f75fccb commit 06f0696

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+25
-22
lines changed

3 files changed

+25
-22
lines changed

‎arch/arm/boot/dts/bcm63178.dtsi

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -32,24 +32,26 @@
3232
next-level-cache = <&L2_0>;
3333
enable-method = "psci";
3434
};
35+
3536
CA7_2: cpu@2 {
3637
device_type = "cpu";
3738
compatible = "arm,cortex-a7";
3839
reg = <0x2>;
3940
next-level-cache = <&L2_0>;
4041
enable-method = "psci";
4142
};
43+
4244
L2_0: l2-cache0 {
4345
compatible = "cache";
4446
};
4547
};
4648

4749
timer {
4850
compatible = "arm,armv7-timer";
49-
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
50-
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
51-
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
52-
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
51+
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
52+
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
53+
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
54+
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
5355
arm,cpu-registers-not-fw-configured;
5456
};
5557

@@ -80,23 +82,23 @@
8082
psci {
8183
compatible = "arm,psci-0.2";
8284
method = "smc";
83-
cpu_off = <1>;
84-
cpu_on = <2>;
8585
};
8686

8787
axi@81000000 {
8888
compatible = "simple-bus";
8989
#address-cells = <1>;
9090
#size-cells = <1>;
91-
ranges = <0 0x81000000 0x4000>;
91+
ranges = <0 0x81000000 0x8000>;
9292

9393
gic: interrupt-controller@1000 {
9494
compatible = "arm,cortex-a7-gic";
9595
#interrupt-cells = <3>;
96-
#address-cells = <0>;
9796
interrupt-controller;
97+
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
9898
reg = <0x1000 0x1000>,
99-
<0x2000 0x2000>;
99+
<0x2000 0x2000>,
100+
<0x4000 0x2000>,
101+
<0x6000 0x2000>;
100102
};
101103
};
102104

‎arch/arm/boot/dts/bcm6846.dtsi

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -40,10 +40,10 @@
4040

4141
timer {
4242
compatible = "arm,armv7-timer";
43-
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
44-
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
45-
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
46-
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
43+
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
44+
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
45+
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
46+
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
4747
arm,cpu-registers-not-fw-configured;
4848
};
4949

@@ -65,23 +65,23 @@
6565
psci {
6666
compatible = "arm,psci-0.2";
6767
method = "smc";
68-
cpu_off = <1>;
69-
cpu_on = <2>;
7068
};
7169

7270
axi@81000000 {
7371
compatible = "simple-bus";
7472
#address-cells = <1>;
7573
#size-cells = <1>;
76-
ranges = <0 0x81000000 0x4000>;
74+
ranges = <0 0x81000000 0x8000>;
7775

7876
gic: interrupt-controller@1000 {
7977
compatible = "arm,cortex-a7-gic";
8078
#interrupt-cells = <3>;
81-
#address-cells = <0>;
8279
interrupt-controller;
80+
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
8381
reg = <0x1000 0x1000>,
84-
<0x2000 0x2000>;
82+
<0x2000 0x2000>,
83+
<0x4000 0x2000>,
84+
<0x6000 0x2000>;
8585
};
8686
};
8787

‎arch/arm/boot/dts/bcm6878.dtsi

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -32,17 +32,18 @@
3232
next-level-cache = <&L2_0>;
3333
enable-method = "psci";
3434
};
35+
3536
L2_0: l2-cache0 {
3637
compatible = "cache";
3738
};
3839
};
3940

4041
timer {
4142
compatible = "arm,armv7-timer";
42-
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
43-
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
44-
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
45-
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
43+
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
44+
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
45+
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
46+
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
4647
arm,cpu-registers-not-fw-configured;
4748
};
4849

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