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lima1002alexdeucher
lima1002
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alexdeucher
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drm/amd/swsmu: add smu 14.0.1 vcn and jpeg msg
add new vcn and jpeg msg v2: squash in updates (Alex) v3: rework code for better compat with other smu14.x variants (Alex) Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: lima1002 <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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-27
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‎drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_ppsmc.h‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -54,14 +54,14 @@
5454
#define PPSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
5555
#define PPSMC_MSG_GetPmfwVersion 0x02 ///< Get PMFW version
5656
#define PPSMC_MSG_GetDriverIfVersion 0x03 ///< Get PMFW_DRIVER_IF version
57-
#define PPSMC_MSG_SPARE0 0x04 ///< SPARE
58-
#define PPSMC_MSG_SPARE1 0x05 ///< SPARE
59-
#define PPSMC_MSG_PowerDownVcn 0x06 ///< Power down VCN
60-
#define PPSMC_MSG_PowerUpVcn 0x07 ///< Power up VCN; VCN is power gated by default
61-
#define PPSMC_MSG_SetHardMinVcn 0x08 ///< For wireless display
57+
#define PPSMC_MSG_PowerDownVcn1 0x04 ///< Power down VCN1
58+
#define PPSMC_MSG_PowerUpVcn1 0x05 ///< Power up VCN1; VCN1 is power gated by default
59+
#define PPSMC_MSG_PowerDownVcn0 0x06 ///< Power down VCN0
60+
#define PPSMC_MSG_PowerUpVcn0 0x07 ///< Power up VCN0; VCN0 is power gated by default
61+
#define PPSMC_MSG_SetHardMinVcn0 0x08 ///< For wireless display
6262
#define PPSMC_MSG_SetSoftMinGfxclk 0x09 ///< Set SoftMin for GFXCLK, argument is frequency in MHz
63-
#define PPSMC_MSG_SPARE2 0x0A ///< SPARE
64-
#define PPSMC_MSG_SPARE3 0x0B ///< SPARE
63+
#define PPSMC_MSG_SetHardMinVcn1 0x0A ///< For wireless display
64+
#define PPSMC_MSG_SetSoftMinVcn1 0x0B ///< Set soft min for VCN1 clocks (VCLK1 and DCLK1)
6565
#define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload
6666
#define PPSMC_MSG_SetDriverDramAddrHigh 0x0D ///< Set high 32 bits of DRAM address for Driver table transfer
6767
#define PPSMC_MSG_SetDriverDramAddrLow 0x0E ///< Set low 32 bits of DRAM address for Driver table transfer
@@ -71,7 +71,7 @@
7171
#define PPSMC_MSG_GetEnabledSmuFeatures 0x12 ///< Get enabled features in PMFW
7272
#define PPSMC_MSG_SetHardMinSocclkByFreq 0x13 ///< Set hard min for SOC CLK
7373
#define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK
74-
#define PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for VCN clocks (VCLK and DCLK)
74+
#define PPSMC_MSG_SetSoftMinVcn0 0x15 ///< Set soft min for VCN0 clocks (VCLK0 and DCLK0)
7575

7676
#define PPSMC_MSG_EnableGfxImu 0x16 ///< Enable GFX IMU
7777

@@ -84,17 +84,17 @@
8484

8585
#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x1D ///< Set soft max for SOC CLK
8686
#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK
87-
#define PPSMC_MSG_SetSoftMaxVcn 0x1F ///< Set soft max for VCN clocks (VCLK and DCLK)
87+
#define PPSMC_MSG_SetSoftMaxVcn0 0x1F ///< Set soft max for VCN0 clocks (VCLK0 and DCLK0)
8888
#define PPSMC_MSG_spare_0x20 0x20
89-
#define PPSMC_MSG_PowerDownJpeg 0x21 ///< Power down Jpeg
90-
#define PPSMC_MSG_PowerUpJpeg 0x22 ///< Power up Jpeg; VCN is power gated by default
89+
#define PPSMC_MSG_PowerDownJpeg0 0x21 ///< Power down Jpeg of VCN0
90+
#define PPSMC_MSG_PowerUpJpeg0 0x22 ///< Power up Jpeg of VCN0; VCN0 is power gated by default
9191

9292
#define PPSMC_MSG_SetHardMinFclkByFreq 0x23 ///< Set hard min for FCLK
9393
#define PPSMC_MSG_SetSoftMinSocclkByFreq 0x24 ///< Set soft min for SOC CLK
9494
#define PPSMC_MSG_AllowZstates 0x25 ///< Inform PMFM of allowing Zstate entry, i.e. no Miracast activity
95-
#define PPSMC_MSG_Reserved 0x26 ///< Not used
96-
#define PPSMC_MSG_Reserved1 0x27 ///< Not used, previously PPSMC_MSG_RequestActiveWgp
97-
#define PPSMC_MSG_Reserved2 0x28 ///< Not used, previously PPSMC_MSG_QueryActiveWgp
95+
#define PPSMC_MSG_PowerDownJpeg1 0x26 ///< Power down Jpeg of VCN1
96+
#define PPSMC_MSG_PowerUpJpeg1 0x27 ///< Power up Jpeg of VCN1; VCN1 is power gated by default
97+
#define PPSMC_MSG_SetSoftMaxVcn1 0x28 ///< Set soft max for VCN1 clocks (VCLK1 and DCLK1)
9898
#define PPSMC_MSG_PowerDownIspByTile 0x29 ///< ISP is power gated by default
9999
#define PPSMC_MSG_PowerUpIspByTile 0x2A ///< This message is used to power up ISP tiles and enable the ISP DPM
100100
#define PPSMC_MSG_SetHardMinIspiclkByFreq 0x2B ///< Set HardMin by frequency for ISPICLK

‎drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -115,6 +115,10 @@
115115
__SMU_DUMMY_MAP(PowerDownVcn), \
116116
__SMU_DUMMY_MAP(PowerUpJpeg), \
117117
__SMU_DUMMY_MAP(PowerDownJpeg), \
118+
__SMU_DUMMY_MAP(PowerUpJpeg0), \
119+
__SMU_DUMMY_MAP(PowerDownJpeg0), \
120+
__SMU_DUMMY_MAP(PowerUpJpeg1), \
121+
__SMU_DUMMY_MAP(PowerDownJpeg1), \
118122
__SMU_DUMMY_MAP(BacoAudioD3PME), \
119123
__SMU_DUMMY_MAP(ArmD3), \
120124
__SMU_DUMMY_MAP(RunDcBtc), \
@@ -135,6 +139,8 @@
135139
__SMU_DUMMY_MAP(PowerUpSdma), \
136140
__SMU_DUMMY_MAP(SetHardMinIspclkByFreq), \
137141
__SMU_DUMMY_MAP(SetHardMinVcn), \
142+
__SMU_DUMMY_MAP(SetHardMinVcn0), \
143+
__SMU_DUMMY_MAP(SetHardMinVcn1), \
138144
__SMU_DUMMY_MAP(SetAllowFclkSwitch), \
139145
__SMU_DUMMY_MAP(SetMinVideoGfxclkFreq), \
140146
__SMU_DUMMY_MAP(ActiveProcessNotify), \
@@ -150,6 +156,8 @@
150156
__SMU_DUMMY_MAP(SetPhyclkVoltageByFreq), \
151157
__SMU_DUMMY_MAP(SetDppclkVoltageByFreq), \
152158
__SMU_DUMMY_MAP(SetSoftMinVcn), \
159+
__SMU_DUMMY_MAP(SetSoftMinVcn0), \
160+
__SMU_DUMMY_MAP(SetSoftMinVcn1), \
153161
__SMU_DUMMY_MAP(EnablePostCode), \
154162
__SMU_DUMMY_MAP(GetGfxclkFrequency), \
155163
__SMU_DUMMY_MAP(GetFclkFrequency), \
@@ -161,6 +169,8 @@
161169
__SMU_DUMMY_MAP(SetSoftMaxSocclkByFreq), \
162170
__SMU_DUMMY_MAP(SetSoftMaxFclkByFreq), \
163171
__SMU_DUMMY_MAP(SetSoftMaxVcn), \
172+
__SMU_DUMMY_MAP(SetSoftMaxVcn0), \
173+
__SMU_DUMMY_MAP(SetSoftMaxVcn1), \
164174
__SMU_DUMMY_MAP(PowerGateMmHub), \
165175
__SMU_DUMMY_MAP(UpdatePmeRestore), \
166176
__SMU_DUMMY_MAP(GpuChangeState), \

‎drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c‎

Lines changed: 44 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1402,9 +1402,22 @@ int smu_v14_0_set_vcn_enable(struct smu_context *smu,
14021402
if (adev->vcn.harvest_config & (1 << i))
14031403
continue;
14041404

1405-
ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1406-
SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1407-
i << 16U, NULL);
1405+
if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||
1406+
amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {
1407+
if (i == 0)
1408+
ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1409+
SMU_MSG_PowerUpVcn0 : SMU_MSG_PowerDownVcn0,
1410+
i << 16U, NULL);
1411+
else if (i == 1)
1412+
ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1413+
SMU_MSG_PowerUpVcn1 : SMU_MSG_PowerDownVcn1,
1414+
i << 16U, NULL);
1415+
} else {
1416+
ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1417+
SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1418+
i << 16U, NULL);
1419+
}
1420+
14081421
if (ret)
14091422
return ret;
14101423
}
@@ -1415,9 +1428,34 @@ int smu_v14_0_set_vcn_enable(struct smu_context *smu,
14151428
int smu_v14_0_set_jpeg_enable(struct smu_context *smu,
14161429
bool enable)
14171430
{
1418-
return smu_cmn_send_smc_msg_with_param(smu, enable ?
1419-
SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
1420-
0, NULL);
1431+
struct amdgpu_device *adev = smu->adev;
1432+
int i, ret = 0;
1433+
1434+
for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
1435+
if (adev->jpeg.harvest_config & (1 << i))
1436+
continue;
1437+
1438+
if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||
1439+
amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {
1440+
if (i == 0)
1441+
ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1442+
SMU_MSG_PowerUpJpeg0 : SMU_MSG_PowerDownJpeg0,
1443+
i << 16U, NULL);
1444+
else if (i == 1 && amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
1445+
ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1446+
SMU_MSG_PowerUpJpeg1 : SMU_MSG_PowerDownJpeg1,
1447+
i << 16U, NULL);
1448+
} else {
1449+
ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1450+
SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
1451+
i << 16U, NULL);
1452+
}
1453+
1454+
if (ret)
1455+
return ret;
1456+
}
1457+
1458+
return ret;
14211459
}
14221460

14231461
int smu_v14_0_run_btc(struct smu_context *smu)

‎drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c‎

Lines changed: 14 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -70,9 +70,12 @@ static struct cmn2asic_msg_mapping smu_v14_0_0_message_map[SMU_MSG_MAX_COUNT] =
7070
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
7171
MSG_MAP(GetSmuVersion, PPSMC_MSG_GetPmfwVersion, 1),
7272
MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
73-
MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
74-
MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
75-
MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
73+
MSG_MAP(PowerDownVcn0, PPSMC_MSG_PowerDownVcn0, 1),
74+
MSG_MAP(PowerUpVcn0, PPSMC_MSG_PowerUpVcn0, 1),
75+
MSG_MAP(SetHardMinVcn0, PPSMC_MSG_SetHardMinVcn0, 1),
76+
MSG_MAP(PowerDownVcn1, PPSMC_MSG_PowerDownVcn1, 1),
77+
MSG_MAP(PowerUpVcn1, PPSMC_MSG_PowerUpVcn1, 1),
78+
MSG_MAP(SetHardMinVcn1, PPSMC_MSG_SetHardMinVcn1, 1),
7679
MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 1),
7780
MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
7881
MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
@@ -83,17 +86,21 @@ static struct cmn2asic_msg_mapping smu_v14_0_0_message_map[SMU_MSG_MAX_COUNT] =
8386
MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1),
8487
MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1),
8588
MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 1),
86-
MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
89+
MSG_MAP(SetSoftMinVcn0, PPSMC_MSG_SetSoftMinVcn0, 1),
90+
MSG_MAP(SetSoftMinVcn1, PPSMC_MSG_SetSoftMinVcn1, 1),
8791
MSG_MAP(EnableGfxImu, PPSMC_MSG_EnableGfxImu, 1),
8892
MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1),
8993
MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1),
9094
MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
9195
MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1),
9296
MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1),
9397
MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1),
94-
MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
95-
MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
96-
MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
98+
MSG_MAP(SetSoftMaxVcn0, PPSMC_MSG_SetSoftMaxVcn0, 1),
99+
MSG_MAP(SetSoftMaxVcn1, PPSMC_MSG_SetSoftMaxVcn1, 1),
100+
MSG_MAP(PowerDownJpeg0, PPSMC_MSG_PowerDownJpeg0, 1),
101+
MSG_MAP(PowerUpJpeg0, PPSMC_MSG_PowerUpJpeg0, 1),
102+
MSG_MAP(PowerDownJpeg1, PPSMC_MSG_PowerDownJpeg1, 1),
103+
MSG_MAP(PowerUpJpeg1, PPSMC_MSG_PowerUpJpeg1, 1),
97104
MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1),
98105
MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 1),
99106
MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1),

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