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23 | 23 |
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24 | 24 | #include <soc/rockchip/rockchip_grf.h>
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25 | 25 | #include <soc/rockchip/rk3399_grf.h>
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| 26 | +#include <soc/rockchip/rk3568_grf.h> |
26 | 27 |
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27 | 28 | #define DMC_MAX_CHANNELS 2
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28 | 29 |
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@@ -211,10 +212,36 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
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211 | 212 | return 0;
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212 | 213 | };
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213 | 214 |
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| 215 | +static int rk3568_dfi_init(struct rockchip_dfi *dfi) |
| 216 | +{ |
| 217 | + struct regmap *regmap_pmu = dfi->regmap_pmu; |
| 218 | + u32 reg2, reg3; |
| 219 | + |
| 220 | + regmap_read(regmap_pmu, RK3568_PMUGRF_OS_REG2, ®2); |
| 221 | + regmap_read(regmap_pmu, RK3568_PMUGRF_OS_REG3, ®3); |
| 222 | + |
| 223 | + /* lower 3 bits of the DDR type */ |
| 224 | + dfi->ddr_type = FIELD_GET(RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2); |
| 225 | + |
| 226 | + /* |
| 227 | + * For version three and higher the upper two bits of the DDR type are |
| 228 | + * in RK3568_PMUGRF_OS_REG3 |
| 229 | + */ |
| 230 | + if (FIELD_GET(RK3568_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3) |
| 231 | + dfi->ddr_type |= FIELD_GET(RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3, reg3) << 3; |
| 232 | + |
| 233 | + dfi->channel_mask = BIT(0); |
| 234 | + dfi->max_channels = 1; |
| 235 | + |
| 236 | + return 0; |
| 237 | +}; |
| 238 | + |
214 | 239 | static const struct of_device_id rockchip_dfi_id_match[] = {
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215 | 240 | { .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init },
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| 241 | + { .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init }, |
216 | 242 | { },
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217 | 243 | };
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| 244 | + |
218 | 245 | MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
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219 | 246 |
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220 | 247 | static int rockchip_dfi_probe(struct platform_device *pdev)
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