106106#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */
107107#define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */
108108#define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */
109+ #define PHY_CNTL1_INIT 0x03900000
110+ #define PHY_INVERT BIT(17)
109111#define HHI_HDMI_PHY_CNTL2 0x3a8 /* 0xea */
110112#define HHI_HDMI_PHY_CNTL3 0x3ac /* 0xeb */
111113#define HHI_HDMI_PHY_CNTL4 0x3b0 /* 0xec */
@@ -130,6 +132,8 @@ struct meson_dw_hdmi_data {
130132 unsigned int addr );
131133 void (* dwc_write )(struct meson_dw_hdmi * dw_hdmi ,
132134 unsigned int addr , unsigned int data );
135+ u32 cntl0_init ;
136+ u32 cntl1_init ;
133137};
134138
135139struct meson_dw_hdmi {
@@ -458,7 +462,9 @@ static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi,
458462
459463 DRM_DEBUG_DRIVER ("\n" );
460464
461- regmap_write (priv -> hhi , HHI_HDMI_PHY_CNTL0 , 0 );
465+ /* Fallback to init mode */
466+ regmap_write (priv -> hhi , HHI_HDMI_PHY_CNTL1 , dw_hdmi -> data -> cntl1_init );
467+ regmap_write (priv -> hhi , HHI_HDMI_PHY_CNTL0 , dw_hdmi -> data -> cntl0_init );
462468}
463469
464470static enum drm_connector_status dw_hdmi_read_hpd (struct dw_hdmi * hdmi ,
@@ -576,18 +582,31 @@ static const struct regmap_config meson_dw_hdmi_regmap_config = {
576582 .fast_io = true,
577583};
578584
579- static const struct meson_dw_hdmi_data meson_dw_hdmi_gx_data = {
585+ static const struct meson_dw_hdmi_data meson_dw_hdmi_gxbb_data = {
580586 .top_read = dw_hdmi_top_read ,
581587 .top_write = dw_hdmi_top_write ,
582588 .dwc_read = dw_hdmi_dwc_read ,
583589 .dwc_write = dw_hdmi_dwc_write ,
590+ .cntl0_init = 0x0 ,
591+ .cntl1_init = PHY_CNTL1_INIT | PHY_INVERT ,
592+ };
593+
594+ static const struct meson_dw_hdmi_data meson_dw_hdmi_gxl_data = {
595+ .top_read = dw_hdmi_top_read ,
596+ .top_write = dw_hdmi_top_write ,
597+ .dwc_read = dw_hdmi_dwc_read ,
598+ .dwc_write = dw_hdmi_dwc_write ,
599+ .cntl0_init = 0x0 ,
600+ .cntl1_init = PHY_CNTL1_INIT ,
584601};
585602
586603static const struct meson_dw_hdmi_data meson_dw_hdmi_g12a_data = {
587604 .top_read = dw_hdmi_g12a_top_read ,
588605 .top_write = dw_hdmi_g12a_top_write ,
589606 .dwc_read = dw_hdmi_g12a_dwc_read ,
590607 .dwc_write = dw_hdmi_g12a_dwc_write ,
608+ .cntl0_init = 0x000b4242 , /* Bandgap */
609+ .cntl1_init = PHY_CNTL1_INIT ,
591610};
592611
593612static void meson_dw_hdmi_init (struct meson_dw_hdmi * meson_dw_hdmi )
@@ -626,18 +645,8 @@ static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi)
626645 meson_dw_hdmi -> data -> top_write (meson_dw_hdmi , HDMITX_TOP_BIST_CNTL , BIT (12 ));
627646
628647 /* Setup PHY */
629- regmap_update_bits (priv -> hhi , HHI_HDMI_PHY_CNTL1 ,
630- 0xffff << 16 , 0x0390 << 16 );
631-
632- /* BIT_INVERT */
633- if (dw_hdmi_is_compatible (meson_dw_hdmi , "amlogic,meson-gxl-dw-hdmi" ) ||
634- dw_hdmi_is_compatible (meson_dw_hdmi , "amlogic,meson-gxm-dw-hdmi" ) ||
635- dw_hdmi_is_compatible (meson_dw_hdmi , "amlogic,meson-g12a-dw-hdmi" ))
636- regmap_update_bits (priv -> hhi , HHI_HDMI_PHY_CNTL1 ,
637- BIT (17 ), 0 );
638- else
639- regmap_update_bits (priv -> hhi , HHI_HDMI_PHY_CNTL1 ,
640- BIT (17 ), BIT (17 ));
648+ regmap_write (priv -> hhi , HHI_HDMI_PHY_CNTL1 , meson_dw_hdmi -> data -> cntl1_init );
649+ regmap_write (priv -> hhi , HHI_HDMI_PHY_CNTL0 , meson_dw_hdmi -> data -> cntl0_init );
641650
642651 /* Enable HDMI-TX Interrupt */
643652 meson_dw_hdmi -> data -> top_write (meson_dw_hdmi , HDMITX_TOP_INTR_STAT_CLR ,
@@ -848,11 +857,11 @@ static const struct dev_pm_ops meson_dw_hdmi_pm_ops = {
848857
849858static const struct of_device_id meson_dw_hdmi_of_table [] = {
850859 { .compatible = "amlogic,meson-gxbb-dw-hdmi" ,
851- .data = & meson_dw_hdmi_gx_data },
860+ .data = & meson_dw_hdmi_gxbb_data },
852861 { .compatible = "amlogic,meson-gxl-dw-hdmi" ,
853- .data = & meson_dw_hdmi_gx_data },
862+ .data = & meson_dw_hdmi_gxl_data },
854863 { .compatible = "amlogic,meson-gxm-dw-hdmi" ,
855- .data = & meson_dw_hdmi_gx_data },
864+ .data = & meson_dw_hdmi_gxl_data },
856865 { .compatible = "amlogic,meson-g12a-dw-hdmi" ,
857866 .data = & meson_dw_hdmi_g12a_data },
858867 { }
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