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bebarinobebarino
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Merge branch 'clk-allwinner' into clk-next
* clk-allwinner: clk: sunxi-ng: sun50i: h6: Modify GPU clock configuration to support DFS clk: sunxi: Do not select the PRCM MFD clk: sunxi: Limit legacy clocks to 32-bit ARM clk: sunxi-ng: Deduplicate ccu_clks arrays
2 parents dfcbbd7 + 432b096 commit 08fc500

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7 files changed

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-295
lines changed

7 files changed

+50
-295
lines changed

‎drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c

Lines changed: 2 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -143,17 +143,6 @@ static struct ccu_common *sun50i_h6_r_ccu_clks[] = {
143143
&w1_clk.common,
144144
};
145145

146-
static struct ccu_common *sun50i_h616_r_ccu_clks[] = {
147-
&r_apb1_clk.common,
148-
&r_apb2_clk.common,
149-
&r_apb1_twd_clk.common,
150-
&r_apb2_i2c_clk.common,
151-
&r_apb2_rsb_clk.common,
152-
&r_apb1_ir_clk.common,
153-
&r_apb1_rtc_clk.common,
154-
&ir_clk.common,
155-
};
156-
157146
static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
158147
.hws = {
159148
[CLK_AR100] = &ar100_clk.common.hw,
@@ -219,8 +208,8 @@ static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
219208
};
220209

221210
static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = {
222-
.ccu_clks = sun50i_h616_r_ccu_clks,
223-
.num_ccu_clks = ARRAY_SIZE(sun50i_h616_r_ccu_clks),
211+
.ccu_clks = sun50i_h6_r_ccu_clks,
212+
.num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks),
224213

225214
.hw_clks = &sun50i_h616_r_hw_clks,
226215

‎drivers/clk/sunxi-ng/ccu-sun50i-h6.c

Lines changed: 13 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -95,13 +95,13 @@ static struct ccu_nkmp pll_periph1_clk = {
9595
},
9696
};
9797

98+
/* For GPU PLL, using an output divider for DFS causes system to fail */
9899
#define SUN50I_H6_PLL_GPU_REG 0x030
99100
static struct ccu_nkmp pll_gpu_clk = {
100101
.enable = BIT(31),
101102
.lock = BIT(28),
102103
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
103104
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
104-
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
105105
.common = {
106106
.reg = 0x030,
107107
.hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
@@ -294,9 +294,9 @@ static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace",
294294
static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2",
295295
0x62c, BIT(0), 0);
296296

297+
/* Keep GPU_CLK divider const to avoid DFS instability. */
297298
static const char * const gpu_parents[] = { "pll-gpu" };
298-
static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
299-
0, 3, /* M */
299+
static SUNXI_CCU_MUX_WITH_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
300300
24, 1, /* mux */
301301
BIT(31), /* gate */
302302
CLK_SET_RATE_PARENT);
@@ -1191,6 +1191,16 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev)
11911191
if (IS_ERR(reg))
11921192
return PTR_ERR(reg);
11931193

1194+
/* Force PLL_GPU output divider bits to 0 */
1195+
val = readl(reg + SUN50I_H6_PLL_GPU_REG);
1196+
val &= ~BIT(0);
1197+
writel(val, reg + SUN50I_H6_PLL_GPU_REG);
1198+
1199+
/* Force GPU_CLK divider bits to 0 */
1200+
val = readl(reg + gpu_clk.common.reg);
1201+
val &= ~GENMASK(3, 0);
1202+
writel(val, reg + gpu_clk.common.reg);
1203+
11941204
/* Enable the lock bits on all PLLs */
11951205
for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
11961206
val = readl(reg + pll_regs[i]);

‎drivers/clk/sunxi-ng/ccu-sun8i-de2.c

Lines changed: 19 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -53,65 +53,26 @@ static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4,
5353
static SUNXI_CCU_M(rot_div_a83_clk, "rot-div", "pll-de", 0x0c, 0x0c, 4,
5454
CLK_SET_RATE_PARENT);
5555

56-
static struct ccu_common *sun8i_a83t_de2_clks[] = {
56+
static struct ccu_common *sun8i_de2_ccu_clks[] = {
5757
&mixer0_clk.common,
5858
&mixer1_clk.common,
5959
&wb_clk.common,
60-
61-
&bus_mixer0_clk.common,
62-
&bus_mixer1_clk.common,
63-
&bus_wb_clk.common,
64-
65-
&mixer0_div_a83_clk.common,
66-
&mixer1_div_a83_clk.common,
67-
&wb_div_a83_clk.common,
68-
69-
&bus_rot_clk.common,
7060
&rot_clk.common,
71-
&rot_div_a83_clk.common,
72-
};
73-
74-
static struct ccu_common *sun8i_h3_de2_clks[] = {
75-
&mixer0_clk.common,
76-
&mixer1_clk.common,
77-
&wb_clk.common,
78-
79-
&bus_mixer0_clk.common,
80-
&bus_mixer1_clk.common,
81-
&bus_wb_clk.common,
82-
83-
&mixer0_div_clk.common,
84-
&mixer1_div_clk.common,
85-
&wb_div_clk.common,
86-
};
87-
88-
static struct ccu_common *sun8i_v3s_de2_clks[] = {
89-
&mixer0_clk.common,
90-
&wb_clk.common,
91-
92-
&bus_mixer0_clk.common,
93-
&bus_wb_clk.common,
94-
95-
&mixer0_div_clk.common,
96-
&wb_div_clk.common,
97-
};
98-
99-
static struct ccu_common *sun50i_a64_de2_clks[] = {
100-
&mixer0_clk.common,
101-
&mixer1_clk.common,
102-
&wb_clk.common,
10361

10462
&bus_mixer0_clk.common,
10563
&bus_mixer1_clk.common,
10664
&bus_wb_clk.common,
65+
&bus_rot_clk.common,
10766

10867
&mixer0_div_clk.common,
10968
&mixer1_div_clk.common,
11069
&wb_div_clk.common,
111-
112-
&bus_rot_clk.common,
113-
&rot_clk.common,
11470
&rot_div_clk.common,
71+
72+
&mixer0_div_a83_clk.common,
73+
&mixer1_div_a83_clk.common,
74+
&wb_div_a83_clk.common,
75+
&rot_div_a83_clk.common,
11576
};
11677

11778
static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
@@ -219,8 +180,8 @@ static struct ccu_reset_map sun50i_h5_de2_resets[] = {
219180
};
220181

221182
static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
222-
.ccu_clks = sun8i_a83t_de2_clks,
223-
.num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks),
183+
.ccu_clks = sun8i_de2_ccu_clks,
184+
.num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks),
224185

225186
.hw_clks = &sun8i_a83t_de2_hw_clks,
226187

@@ -229,8 +190,8 @@ static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
229190
};
230191

231192
static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
232-
.ccu_clks = sun8i_h3_de2_clks,
233-
.num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
193+
.ccu_clks = sun8i_de2_ccu_clks,
194+
.num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks),
234195

235196
.hw_clks = &sun8i_h3_de2_hw_clks,
236197

@@ -239,8 +200,8 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
239200
};
240201

241202
static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = {
242-
.ccu_clks = sun50i_a64_de2_clks,
243-
.num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
203+
.ccu_clks = sun8i_de2_ccu_clks,
204+
.num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks),
244205

245206
.hw_clks = &sun50i_a64_de2_hw_clks,
246207

@@ -249,8 +210,8 @@ static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = {
249210
};
250211

251212
static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
252-
.ccu_clks = sun8i_v3s_de2_clks,
253-
.num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks),
213+
.ccu_clks = sun8i_de2_ccu_clks,
214+
.num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks),
254215

255216
.hw_clks = &sun8i_v3s_de2_hw_clks,
256217

@@ -259,8 +220,8 @@ static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
259220
};
260221

261222
static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
262-
.ccu_clks = sun50i_a64_de2_clks,
263-
.num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
223+
.ccu_clks = sun8i_de2_ccu_clks,
224+
.num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks),
264225

265226
.hw_clks = &sun50i_a64_de2_hw_clks,
266227

@@ -269,8 +230,8 @@ static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
269230
};
270231

271232
static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
272-
.ccu_clks = sun8i_h3_de2_clks,
273-
.num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
233+
.ccu_clks = sun8i_de2_ccu_clks,
234+
.num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks),
274235

275236
.hw_clks = &sun8i_h3_de2_hw_clks,
276237

‎drivers/clk/sunxi-ng/ccu-sun8i-h3.c

Lines changed: 3 additions & 110 deletions
Original file line numberDiff line numberDiff line change
@@ -562,6 +562,7 @@ static struct ccu_common *sun8i_h3_ccu_clks[] = {
562562
&bus_uart2_clk.common,
563563
&bus_uart3_clk.common,
564564
&bus_scr0_clk.common,
565+
&bus_scr1_clk.common,
565566
&bus_ephy_clk.common,
566567
&bus_dbg_clk.common,
567568
&ths_clk.common,
@@ -612,114 +613,6 @@ static struct ccu_common *sun8i_h3_ccu_clks[] = {
612613
&gpu_clk.common,
613614
};
614615

615-
static struct ccu_common *sun50i_h5_ccu_clks[] = {
616-
&pll_cpux_clk.common,
617-
&pll_audio_base_clk.common,
618-
&pll_video_clk.common,
619-
&pll_ve_clk.common,
620-
&pll_ddr_clk.common,
621-
&pll_periph0_clk.common,
622-
&pll_gpu_clk.common,
623-
&pll_periph1_clk.common,
624-
&pll_de_clk.common,
625-
&cpux_clk.common,
626-
&axi_clk.common,
627-
&ahb1_clk.common,
628-
&apb1_clk.common,
629-
&apb2_clk.common,
630-
&ahb2_clk.common,
631-
&bus_ce_clk.common,
632-
&bus_dma_clk.common,
633-
&bus_mmc0_clk.common,
634-
&bus_mmc1_clk.common,
635-
&bus_mmc2_clk.common,
636-
&bus_nand_clk.common,
637-
&bus_dram_clk.common,
638-
&bus_emac_clk.common,
639-
&bus_ts_clk.common,
640-
&bus_hstimer_clk.common,
641-
&bus_spi0_clk.common,
642-
&bus_spi1_clk.common,
643-
&bus_otg_clk.common,
644-
&bus_ehci0_clk.common,
645-
&bus_ehci1_clk.common,
646-
&bus_ehci2_clk.common,
647-
&bus_ehci3_clk.common,
648-
&bus_ohci0_clk.common,
649-
&bus_ohci1_clk.common,
650-
&bus_ohci2_clk.common,
651-
&bus_ohci3_clk.common,
652-
&bus_ve_clk.common,
653-
&bus_tcon0_clk.common,
654-
&bus_tcon1_clk.common,
655-
&bus_deinterlace_clk.common,
656-
&bus_csi_clk.common,
657-
&bus_tve_clk.common,
658-
&bus_hdmi_clk.common,
659-
&bus_de_clk.common,
660-
&bus_gpu_clk.common,
661-
&bus_msgbox_clk.common,
662-
&bus_spinlock_clk.common,
663-
&bus_codec_clk.common,
664-
&bus_spdif_clk.common,
665-
&bus_pio_clk.common,
666-
&bus_ths_clk.common,
667-
&bus_i2s0_clk.common,
668-
&bus_i2s1_clk.common,
669-
&bus_i2s2_clk.common,
670-
&bus_i2c0_clk.common,
671-
&bus_i2c1_clk.common,
672-
&bus_i2c2_clk.common,
673-
&bus_uart0_clk.common,
674-
&bus_uart1_clk.common,
675-
&bus_uart2_clk.common,
676-
&bus_uart3_clk.common,
677-
&bus_scr0_clk.common,
678-
&bus_scr1_clk.common,
679-
&bus_ephy_clk.common,
680-
&bus_dbg_clk.common,
681-
&ths_clk.common,
682-
&nand_clk.common,
683-
&mmc0_clk.common,
684-
&mmc1_clk.common,
685-
&mmc2_clk.common,
686-
&ts_clk.common,
687-
&ce_clk.common,
688-
&spi0_clk.common,
689-
&spi1_clk.common,
690-
&i2s0_clk.common,
691-
&i2s1_clk.common,
692-
&i2s2_clk.common,
693-
&spdif_clk.common,
694-
&usb_phy0_clk.common,
695-
&usb_phy1_clk.common,
696-
&usb_phy2_clk.common,
697-
&usb_phy3_clk.common,
698-
&usb_ohci0_clk.common,
699-
&usb_ohci1_clk.common,
700-
&usb_ohci2_clk.common,
701-
&usb_ohci3_clk.common,
702-
&dram_clk.common,
703-
&dram_ve_clk.common,
704-
&dram_csi_clk.common,
705-
&dram_deinterlace_clk.common,
706-
&dram_ts_clk.common,
707-
&de_clk.common,
708-
&tcon_clk.common,
709-
&tve_clk.common,
710-
&deinterlace_clk.common,
711-
&csi_misc_clk.common,
712-
&csi_sclk_clk.common,
713-
&csi_mclk_clk.common,
714-
&ve_clk.common,
715-
&ac_dig_clk.common,
716-
&avs_clk.common,
717-
&hdmi_clk.common,
718-
&hdmi_ddc_clk.common,
719-
&mbus_clk.common,
720-
&gpu_clk.common,
721-
};
722-
723616
static const struct clk_hw *clk_parent_pll_audio[] = {
724617
&pll_audio_base_clk.common.hw
725618
};
@@ -1116,8 +1009,8 @@ static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
11161009
};
11171010

11181011
static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
1119-
.ccu_clks = sun50i_h5_ccu_clks,
1120-
.num_ccu_clks = ARRAY_SIZE(sun50i_h5_ccu_clks),
1012+
.ccu_clks = sun8i_h3_ccu_clks,
1013+
.num_ccu_clks = ARRAY_SIZE(sun8i_h3_ccu_clks),
11211014

11221015
.hw_clks = &sun50i_h5_hw_clks,
11231016

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