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201 | 201 | reset-gpios = <&main_gpio0 44 GPIO_ACTIVE_LOW>;
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202 | 202 | reset-assert-us = <1000>;
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203 | 203 | reset-deassert-us = <1000>;
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204 |
| - ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
205 |
| - ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
206 | 204 | ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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207 | 205 | ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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208 | 206 | };
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230 | 228 | reset-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>;
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231 | 229 | reset-assert-us = <1000>;
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232 | 230 | reset-deassert-us = <1000>;
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233 |
| - ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
234 |
| - ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
235 | 231 | ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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236 | 232 | ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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237 | 233 | };
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242 | 238 | reset-gpios = <&main_gpio1 51 GPIO_ACTIVE_LOW>;
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243 | 239 | reset-assert-us = <1000>;
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244 | 240 | reset-deassert-us = <1000>;
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245 |
| - ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
246 |
| - ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
247 | 241 | ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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248 | 242 | ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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249 | 243 | };
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