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| 1 | +/* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | +/* |
| 3 | + * R-Car RPC Interface Registers Definitions |
| 4 | + * |
| 5 | + * Copyright (C) 2025 Renesas Electronics Corporation |
| 6 | + */ |
| 7 | + |
| 8 | +#ifndef __RENESAS_RPC_IF_REGS_H__ |
| 9 | +#define __RENESAS_RPC_IF_REGS_H__ |
| 10 | + |
| 11 | +#include <linux/bits.h> |
| 12 | + |
| 13 | +#define RPCIF_CMNCR 0x0000 /* R/W */ |
| 14 | +#define RPCIF_CMNCR_MD BIT(31) |
| 15 | +#define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22) |
| 16 | +#define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20) |
| 17 | +#define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18) |
| 18 | +#define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16) |
| 19 | +#define RPCIF_CMNCR_MOIIO(val) (RPCIF_CMNCR_MOIIO0(val) | RPCIF_CMNCR_MOIIO1(val) | \ |
| 20 | + RPCIF_CMNCR_MOIIO2(val) | RPCIF_CMNCR_MOIIO3(val)) |
| 21 | +#define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* documented for RZ/G2L */ |
| 22 | +#define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* documented for RZ/G2L */ |
| 23 | +#define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8) |
| 24 | +#define RPCIF_CMNCR_IOFV(val) (RPCIF_CMNCR_IO0FV(val) | RPCIF_CMNCR_IO2FV(val) | \ |
| 25 | + RPCIF_CMNCR_IO3FV(val)) |
| 26 | +#define RPCIF_CMNCR_BSZ(val) (((val) & 0x3) << 0) |
| 27 | + |
| 28 | +#define RPCIF_SSLDR 0x0004 /* R/W */ |
| 29 | +#define RPCIF_SSLDR_SPNDL(d) (((d) & 0x7) << 16) |
| 30 | +#define RPCIF_SSLDR_SLNDL(d) (((d) & 0x7) << 8) |
| 31 | +#define RPCIF_SSLDR_SCKDL(d) (((d) & 0x7) << 0) |
| 32 | + |
| 33 | +#define RPCIF_DRCR 0x000C /* R/W */ |
| 34 | +#define RPCIF_DRCR_SSLN BIT(24) |
| 35 | +#define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16) |
| 36 | +#define RPCIF_DRCR_RCF BIT(9) |
| 37 | +#define RPCIF_DRCR_RBE BIT(8) |
| 38 | +#define RPCIF_DRCR_SSLE BIT(0) |
| 39 | + |
| 40 | +#define RPCIF_DRCMR 0x0010 /* R/W */ |
| 41 | +#define RPCIF_DRCMR_CMD(c) (((c) & 0xFF) << 16) |
| 42 | +#define RPCIF_DRCMR_OCMD(c) (((c) & 0xFF) << 0) |
| 43 | + |
| 44 | +#define RPCIF_DREAR 0x0014 /* R/W */ |
| 45 | +#define RPCIF_DREAR_EAV(c) (((c) & 0xF) << 16) |
| 46 | +#define RPCIF_DREAR_EAC(c) (((c) & 0x7) << 0) |
| 47 | + |
| 48 | +#define RPCIF_DROPR 0x0018 /* R/W */ |
| 49 | + |
| 50 | +#define RPCIF_DRENR 0x001C /* R/W */ |
| 51 | +#define RPCIF_DRENR_CDB(o) (((u32)((o) & 0x3)) << 30) |
| 52 | +#define RPCIF_DRENR_OCDB(o) (((o) & 0x3) << 28) |
| 53 | +#define RPCIF_DRENR_ADB(o) (((o) & 0x3) << 24) |
| 54 | +#define RPCIF_DRENR_OPDB(o) (((o) & 0x3) << 20) |
| 55 | +#define RPCIF_DRENR_DRDB(o) (((o) & 0x3) << 16) |
| 56 | +#define RPCIF_DRENR_DME BIT(15) |
| 57 | +#define RPCIF_DRENR_CDE BIT(14) |
| 58 | +#define RPCIF_DRENR_OCDE BIT(12) |
| 59 | +#define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8) |
| 60 | +#define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4) |
| 61 | + |
| 62 | +#define RPCIF_SMCR 0x0020 /* R/W */ |
| 63 | +#define RPCIF_SMCR_SSLKP BIT(8) |
| 64 | +#define RPCIF_SMCR_SPIRE BIT(2) |
| 65 | +#define RPCIF_SMCR_SPIWE BIT(1) |
| 66 | +#define RPCIF_SMCR_SPIE BIT(0) |
| 67 | + |
| 68 | +#define RPCIF_SMCMR 0x0024 /* R/W */ |
| 69 | +#define RPCIF_SMCMR_CMD(c) (((c) & 0xFF) << 16) |
| 70 | +#define RPCIF_SMCMR_OCMD(c) (((c) & 0xFF) << 0) |
| 71 | + |
| 72 | +#define RPCIF_SMADR 0x0028 /* R/W */ |
| 73 | + |
| 74 | +#define RPCIF_SMOPR 0x002C /* R/W */ |
| 75 | +#define RPCIF_SMOPR_OPD3(o) (((o) & 0xFF) << 24) |
| 76 | +#define RPCIF_SMOPR_OPD2(o) (((o) & 0xFF) << 16) |
| 77 | +#define RPCIF_SMOPR_OPD1(o) (((o) & 0xFF) << 8) |
| 78 | +#define RPCIF_SMOPR_OPD0(o) (((o) & 0xFF) << 0) |
| 79 | + |
| 80 | +#define RPCIF_SMENR 0x0030 /* R/W */ |
| 81 | +#define RPCIF_SMENR_CDB(o) (((o) & 0x3) << 30) |
| 82 | +#define RPCIF_SMENR_OCDB(o) (((o) & 0x3) << 28) |
| 83 | +#define RPCIF_SMENR_ADB(o) (((o) & 0x3) << 24) |
| 84 | +#define RPCIF_SMENR_OPDB(o) (((o) & 0x3) << 20) |
| 85 | +#define RPCIF_SMENR_SPIDB(o) (((o) & 0x3) << 16) |
| 86 | +#define RPCIF_SMENR_DME BIT(15) |
| 87 | +#define RPCIF_SMENR_CDE BIT(14) |
| 88 | +#define RPCIF_SMENR_OCDE BIT(12) |
| 89 | +#define RPCIF_SMENR_ADE(v) (((v) & 0xF) << 8) |
| 90 | +#define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4) |
| 91 | +#define RPCIF_SMENR_SPIDE(v) (((v) & 0xF) << 0) |
| 92 | + |
| 93 | +#define RPCIF_SMRDR0 0x0038 /* R */ |
| 94 | +#define RPCIF_SMRDR1 0x003C /* R */ |
| 95 | +#define RPCIF_SMWDR0 0x0040 /* W */ |
| 96 | +#define RPCIF_SMWDR1 0x0044 /* W */ |
| 97 | + |
| 98 | +#define RPCIF_CMNSR 0x0048 /* R */ |
| 99 | +#define RPCIF_CMNSR_SSLF BIT(1) |
| 100 | +#define RPCIF_CMNSR_TEND BIT(0) |
| 101 | + |
| 102 | +#define RPCIF_DRDMCR 0x0058 /* R/W */ |
| 103 | +#define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0) |
| 104 | + |
| 105 | +#define RPCIF_DRDRENR 0x005C /* R/W */ |
| 106 | +#define RPCIF_DRDRENR_HYPE(v) (((v) & 0x7) << 12) |
| 107 | +#define RPCIF_DRDRENR_ADDRE BIT(8) |
| 108 | +#define RPCIF_DRDRENR_OPDRE BIT(4) |
| 109 | +#define RPCIF_DRDRENR_DRDRE BIT(0) |
| 110 | + |
| 111 | +#define RPCIF_SMDMCR 0x0060 /* R/W */ |
| 112 | +#define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0) |
| 113 | + |
| 114 | +#define RPCIF_SMDRENR 0x0064 /* R/W */ |
| 115 | +#define RPCIF_SMDRENR_HYPE(v) (((v) & 0x7) << 12) |
| 116 | +#define RPCIF_SMDRENR_ADDRE BIT(8) |
| 117 | +#define RPCIF_SMDRENR_OPDRE BIT(4) |
| 118 | +#define RPCIF_SMDRENR_SPIDRE BIT(0) |
| 119 | + |
| 120 | +#define RPCIF_PHYADD 0x0070 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */ |
| 121 | +#define RPCIF_PHYWR 0x0074 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */ |
| 122 | + |
| 123 | +#define RPCIF_PHYCNT 0x007C /* R/W */ |
| 124 | +#define RPCIF_PHYCNT_CAL BIT(31) |
| 125 | +#define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22) |
| 126 | +#define RPCIF_PHYCNT_EXDS BIT(21) |
| 127 | +#define RPCIF_PHYCNT_OCT BIT(20) |
| 128 | +#define RPCIF_PHYCNT_DDRCAL BIT(19) |
| 129 | +#define RPCIF_PHYCNT_HS BIT(18) |
| 130 | +#define RPCIF_PHYCNT_CKSEL(v) (((v) & 0x3) << 16) /* valid only for RZ/G2L */ |
| 131 | +#define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15 | ((v) & 0x8) << 24) /* valid for R-Car and RZ/G2{E,H,M,N} */ |
| 132 | + |
| 133 | +#define RPCIF_PHYCNT_WBUF2 BIT(4) |
| 134 | +#define RPCIF_PHYCNT_WBUF BIT(2) |
| 135 | +#define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0) |
| 136 | +#define RPCIF_PHYCNT_PHYMEM_MASK GENMASK(1, 0) |
| 137 | + |
| 138 | +#define RPCIF_PHYOFFSET1 0x0080 /* R/W */ |
| 139 | +#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28) |
| 140 | + |
| 141 | +#define RPCIF_PHYOFFSET2 0x0084 /* R/W */ |
| 142 | +#define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8) |
| 143 | + |
| 144 | +#define RPCIF_PHYINT 0x0088 /* R/W */ |
| 145 | +#define RPCIF_PHYINT_WPVAL BIT(1) |
| 146 | + |
| 147 | +#endif /* __RENESAS_RPC_IF_REGS_H__ */ |
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