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jbloomfi-inteljbloomfi-intel
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drm/i915: Rename gen7 cmdparser tables
We're about to introduce some new tables for later gens, and the current naming for the gen7 tables will no longer make sense. v2: rebase Signed-off-by: Jon Bloomfield <[email protected]> Cc: Tony Luck <[email protected]> Cc: Dave Airlie <[email protected]> Cc: Takashi Iwai <[email protected]> Cc: Tyler Hicks <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Reviewed-by: Chris Wilson <[email protected]>
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‎drivers/gpu/drm/i915/i915_cmd_parser.c

Lines changed: 35 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -213,7 +213,7 @@ struct drm_i915_cmd_table {
213213

214214
/* Command Mask Fixed Len Action
215215
---------------------------------------------------------- */
216-
static const struct drm_i915_cmd_descriptor common_cmds[] = {
216+
static const struct drm_i915_cmd_descriptor gen7_common_cmds[] = {
217217
CMD( MI_NOOP, SMI, F, 1, S ),
218218
CMD( MI_USER_INTERRUPT, SMI, F, 1, R ),
219219
CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, M ),
@@ -246,7 +246,7 @@ static const struct drm_i915_cmd_descriptor common_cmds[] = {
246246
CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
247247
};
248248

249-
static const struct drm_i915_cmd_descriptor render_cmds[] = {
249+
static const struct drm_i915_cmd_descriptor gen7_render_cmds[] = {
250250
CMD( MI_FLUSH, SMI, F, 1, S ),
251251
CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
252252
CMD( MI_PREDICATE, SMI, F, 1, S ),
@@ -330,7 +330,7 @@ static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
330330
CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ),
331331
};
332332

333-
static const struct drm_i915_cmd_descriptor video_cmds[] = {
333+
static const struct drm_i915_cmd_descriptor gen7_video_cmds[] = {
334334
CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
335335
CMD( MI_SET_APPID, SMI, F, 1, S ),
336336
CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
@@ -374,7 +374,7 @@ static const struct drm_i915_cmd_descriptor video_cmds[] = {
374374
CMD( MFX_WAIT, SMFX, F, 1, S ),
375375
};
376376

377-
static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
377+
static const struct drm_i915_cmd_descriptor gen7_vecs_cmds[] = {
378378
CMD( MI_ARB_ON_OFF, SMI, F, 1, R ),
379379
CMD( MI_SET_APPID, SMI, F, 1, S ),
380380
CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B,
@@ -412,7 +412,7 @@ static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
412412
}}, ),
413413
};
414414

415-
static const struct drm_i915_cmd_descriptor blt_cmds[] = {
415+
static const struct drm_i915_cmd_descriptor gen7_blt_cmds[] = {
416416
CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ),
417417
CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B,
418418
.bits = {{
@@ -465,35 +465,35 @@ static const struct drm_i915_cmd_descriptor noop_desc =
465465
#undef B
466466
#undef M
467467

468-
static const struct drm_i915_cmd_table gen7_render_cmds[] = {
469-
{ common_cmds, ARRAY_SIZE(common_cmds) },
470-
{ render_cmds, ARRAY_SIZE(render_cmds) },
468+
static const struct drm_i915_cmd_table gen7_render_cmd_table[] = {
469+
{ gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
470+
{ gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) },
471471
};
472472

473-
static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = {
474-
{ common_cmds, ARRAY_SIZE(common_cmds) },
475-
{ render_cmds, ARRAY_SIZE(render_cmds) },
473+
static const struct drm_i915_cmd_table hsw_render_ring_cmd_table[] = {
474+
{ gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
475+
{ gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) },
476476
{ hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
477477
};
478478

479-
static const struct drm_i915_cmd_table gen7_video_cmds[] = {
480-
{ common_cmds, ARRAY_SIZE(common_cmds) },
481-
{ video_cmds, ARRAY_SIZE(video_cmds) },
479+
static const struct drm_i915_cmd_table gen7_video_cmd_table[] = {
480+
{ gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
481+
{ gen7_video_cmds, ARRAY_SIZE(gen7_video_cmds) },
482482
};
483483

484-
static const struct drm_i915_cmd_table hsw_vebox_cmds[] = {
485-
{ common_cmds, ARRAY_SIZE(common_cmds) },
486-
{ vecs_cmds, ARRAY_SIZE(vecs_cmds) },
484+
static const struct drm_i915_cmd_table hsw_vebox_cmd_table[] = {
485+
{ gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
486+
{ gen7_vecs_cmds, ARRAY_SIZE(gen7_vecs_cmds) },
487487
};
488488

489-
static const struct drm_i915_cmd_table gen7_blt_cmds[] = {
490-
{ common_cmds, ARRAY_SIZE(common_cmds) },
491-
{ blt_cmds, ARRAY_SIZE(blt_cmds) },
489+
static const struct drm_i915_cmd_table gen7_blt_cmd_table[] = {
490+
{ gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
491+
{ gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) },
492492
};
493493

494-
static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
495-
{ common_cmds, ARRAY_SIZE(common_cmds) },
496-
{ blt_cmds, ARRAY_SIZE(blt_cmds) },
494+
static const struct drm_i915_cmd_table hsw_blt_ring_cmd_table[] = {
495+
{ gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) },
496+
{ gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) },
497497
{ hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
498498
};
499499

@@ -873,12 +873,12 @@ void intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
873873
switch (engine->class) {
874874
case RENDER_CLASS:
875875
if (IS_HASWELL(engine->i915)) {
876-
cmd_tables = hsw_render_ring_cmds;
876+
cmd_tables = hsw_render_ring_cmd_table;
877877
cmd_table_count =
878-
ARRAY_SIZE(hsw_render_ring_cmds);
878+
ARRAY_SIZE(hsw_render_ring_cmd_table);
879879
} else {
880-
cmd_tables = gen7_render_cmds;
881-
cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
880+
cmd_tables = gen7_render_cmd_table;
881+
cmd_table_count = ARRAY_SIZE(gen7_render_cmd_table);
882882
}
883883

884884
if (IS_HASWELL(engine->i915)) {
@@ -892,17 +892,17 @@ void intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
892892
engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
893893
break;
894894
case VIDEO_DECODE_CLASS:
895-
cmd_tables = gen7_video_cmds;
896-
cmd_table_count = ARRAY_SIZE(gen7_video_cmds);
895+
cmd_tables = gen7_video_cmd_table;
896+
cmd_table_count = ARRAY_SIZE(gen7_video_cmd_table);
897897
engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
898898
break;
899899
case COPY_ENGINE_CLASS:
900900
if (IS_HASWELL(engine->i915)) {
901-
cmd_tables = hsw_blt_ring_cmds;
902-
cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
901+
cmd_tables = hsw_blt_ring_cmd_table;
902+
cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmd_table);
903903
} else {
904-
cmd_tables = gen7_blt_cmds;
905-
cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
904+
cmd_tables = gen7_blt_cmd_table;
905+
cmd_table_count = ARRAY_SIZE(gen7_blt_cmd_table);
906906
}
907907

908908
if (IS_HASWELL(engine->i915)) {
@@ -916,8 +916,8 @@ void intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
916916
engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
917917
break;
918918
case VIDEO_ENHANCEMENT_CLASS:
919-
cmd_tables = hsw_vebox_cmds;
920-
cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds);
919+
cmd_tables = hsw_vebox_cmd_table;
920+
cmd_table_count = ARRAY_SIZE(hsw_vebox_cmd_table);
921921
/* VECS can use the same length_mask function as VCS */
922922
engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
923923
break;

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