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clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid
Fixed ops were already identical, this adds support for non-fixed ops by sharing between trion and lucid. This also changes the names for trion ops to be consistent with the rest. Note LUCID_PCAL_DONE is renamed to TRION_PCAL_DONE because it is wrong for lucid, LUCID_PCAL_DONE should be BIT(27). Next patch will address this. Signed-off-by: Jonathan Marek <[email protected]> Tested-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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+32
-51
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3 files changed

+32
-51
lines changed

‎drivers/clk/qcom/clk-alpha-pll.c

Lines changed: 17 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -101,21 +101,6 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
101101
[PLL_OFF_FRAC] = 0x38,
102102
},
103103
[CLK_ALPHA_PLL_TYPE_TRION] = {
104-
[PLL_OFF_L_VAL] = 0x04,
105-
[PLL_OFF_CAL_L_VAL] = 0x08,
106-
[PLL_OFF_USER_CTL] = 0x0c,
107-
[PLL_OFF_USER_CTL_U] = 0x10,
108-
[PLL_OFF_USER_CTL_U1] = 0x14,
109-
[PLL_OFF_CONFIG_CTL] = 0x18,
110-
[PLL_OFF_CONFIG_CTL_U] = 0x1c,
111-
[PLL_OFF_CONFIG_CTL_U1] = 0x20,
112-
[PLL_OFF_TEST_CTL] = 0x24,
113-
[PLL_OFF_TEST_CTL_U] = 0x28,
114-
[PLL_OFF_STATUS] = 0x30,
115-
[PLL_OFF_OPMODE] = 0x38,
116-
[PLL_OFF_ALPHA_VAL] = 0x40,
117-
},
118-
[CLK_ALPHA_PLL_TYPE_LUCID] = {
119104
[PLL_OFF_L_VAL] = 0x04,
120105
[PLL_OFF_CAL_L_VAL] = 0x08,
121106
[PLL_OFF_USER_CTL] = 0x0c,
@@ -154,9 +139,9 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
154139
#define PLL_OUT_MASK 0x7
155140
#define PLL_RATE_MARGIN 500
156141

157-
/* LUCID PLL specific settings and offsets */
158-
#define LUCID_PLL_CAL_VAL 0x44
159-
#define LUCID_PCAL_DONE BIT(26)
142+
/* TRION PLL specific settings and offsets */
143+
#define TRION_PLL_CAL_VAL 0x44
144+
#define TRION_PCAL_DONE BIT(26)
160145

161146
#define pll_alpha_width(p) \
162147
((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
@@ -910,14 +895,14 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = {
910895
};
911896
EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
912897

913-
const struct clk_ops clk_trion_fixed_pll_ops = {
898+
const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
914899
.enable = clk_trion_pll_enable,
915900
.disable = clk_trion_pll_disable,
916901
.is_enabled = clk_trion_pll_is_enabled,
917902
.recalc_rate = clk_trion_pll_recalc_rate,
918903
.round_rate = clk_alpha_pll_round_rate,
919904
};
920-
EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);
905+
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);
921906

922907
static unsigned long
923908
clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
@@ -1337,12 +1322,12 @@ clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
13371322
val << PLL_POST_DIV_SHIFT);
13381323
}
13391324

1340-
const struct clk_ops clk_trion_pll_postdiv_ops = {
1325+
const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
13411326
.recalc_rate = clk_trion_pll_postdiv_recalc_rate,
13421327
.round_rate = clk_trion_pll_postdiv_round_rate,
13431328
.set_rate = clk_trion_pll_postdiv_set_rate,
13441329
};
1345-
EXPORT_SYMBOL_GPL(clk_trion_pll_postdiv_ops);
1330+
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);
13461331

13471332
static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
13481333
unsigned long rate, unsigned long *prate)
@@ -1397,13 +1382,13 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
13971382
* @regmap: register map
13981383
* @config: configuration to apply for pll
13991384
*/
1400-
void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1385+
void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
14011386
const struct alpha_pll_config *config)
14021387
{
14031388
if (config->l)
14041389
regmap_write(regmap, PLL_L_VAL(pll), config->l);
14051390

1406-
regmap_write(regmap, PLL_CAL_L_VAL(pll), LUCID_PLL_CAL_VAL);
1391+
regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
14071392

14081393
if (config->alpha)
14091394
regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
@@ -1456,21 +1441,21 @@ void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
14561441
/* Place the PLL in STANDBY mode */
14571442
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
14581443
}
1459-
EXPORT_SYMBOL_GPL(clk_lucid_pll_configure);
1444+
EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
14601445

14611446
/*
1462-
* The Lucid PLL requires a power-on self-calibration which happens when the
1447+
* The TRION PLL requires a power-on self-calibration which happens when the
14631448
* PLL comes out of reset. Calibrate in case it is not completed.
14641449
*/
1465-
static int alpha_pll_lucid_prepare(struct clk_hw *hw)
1450+
static int alpha_pll_trion_prepare(struct clk_hw *hw)
14661451
{
14671452
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
14681453
u32 regval;
14691454
int ret;
14701455

14711456
/* Return early if calibration is not needed. */
14721457
regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &regval);
1473-
if (regval & LUCID_PCAL_DONE)
1458+
if (regval & TRION_PCAL_DONE)
14741459
return 0;
14751460

14761461
/* On/off to calibrate */
@@ -1481,7 +1466,7 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw)
14811466
return ret;
14821467
}
14831468

1484-
static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate,
1469+
static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
14851470
unsigned long prate)
14861471
{
14871472
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
@@ -1535,26 +1520,17 @@ static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate,
15351520
return 0;
15361521
}
15371522

1538-
const struct clk_ops clk_alpha_pll_lucid_ops = {
1539-
.prepare = alpha_pll_lucid_prepare,
1523+
const struct clk_ops clk_alpha_pll_trion_ops = {
1524+
.prepare = alpha_pll_trion_prepare,
15401525
.enable = clk_trion_pll_enable,
15411526
.disable = clk_trion_pll_disable,
15421527
.is_enabled = clk_trion_pll_is_enabled,
15431528
.recalc_rate = clk_trion_pll_recalc_rate,
15441529
.round_rate = clk_alpha_pll_round_rate,
1545-
.set_rate = alpha_pll_lucid_set_rate,
1530+
.set_rate = alpha_pll_trion_set_rate,
15461531
};
15471532
EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
15481533

1549-
const struct clk_ops clk_alpha_pll_fixed_lucid_ops = {
1550-
.enable = clk_trion_pll_enable,
1551-
.disable = clk_trion_pll_disable,
1552-
.is_enabled = clk_trion_pll_is_enabled,
1553-
.recalc_rate = clk_trion_pll_recalc_rate,
1554-
.round_rate = clk_alpha_pll_round_rate,
1555-
};
1556-
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_ops);
1557-
15581534
const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
15591535
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
15601536
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,

‎drivers/clk/qcom/clk-alpha-pll.h

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ enum {
1414
CLK_ALPHA_PLL_TYPE_BRAMMO,
1515
CLK_ALPHA_PLL_TYPE_FABIA,
1616
CLK_ALPHA_PLL_TYPE_TRION,
17-
CLK_ALPHA_PLL_TYPE_LUCID,
17+
CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
1818
CLK_ALPHA_PLL_TYPE_MAX,
1919
};
2020

@@ -134,18 +134,23 @@ extern const struct clk_ops clk_alpha_pll_fabia_ops;
134134
extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
135135
extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
136136

137-
extern const struct clk_ops clk_alpha_pll_lucid_ops;
138-
extern const struct clk_ops clk_alpha_pll_fixed_lucid_ops;
137+
extern const struct clk_ops clk_alpha_pll_trion_ops;
138+
extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;
139+
extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;
140+
141+
#define clk_alpha_pll_lucid_ops clk_alpha_pll_trion_ops
142+
#define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
139143
extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
140144

141145
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
142146
const struct alpha_pll_config *config);
143147
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
144148
const struct alpha_pll_config *config);
145-
void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
149+
void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
146150
const struct alpha_pll_config *config);
151+
#define clk_lucid_pll_configure(pll, regmap, config) \
152+
clk_trion_pll_configure(pll, regmap, config)
153+
147154

148-
extern const struct clk_ops clk_trion_fixed_pll_ops;
149-
extern const struct clk_ops clk_trion_pll_postdiv_ops;
150155

151156
#endif

‎drivers/clk/qcom/gcc-sm8150.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ static struct clk_alpha_pll gpll0 = {
5353
.name = "bi_tcxo",
5454
},
5555
.num_parents = 1,
56-
.ops = &clk_trion_fixed_pll_ops,
56+
.ops = &clk_alpha_pll_fixed_trion_ops,
5757
},
5858
},
5959
};
@@ -79,7 +79,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = {
7979
.hw = &gpll0.clkr.hw,
8080
},
8181
.num_parents = 1,
82-
.ops = &clk_trion_pll_postdiv_ops,
82+
.ops = &clk_alpha_pll_postdiv_trion_ops,
8383
},
8484
};
8585

@@ -98,7 +98,7 @@ static struct clk_alpha_pll gpll7 = {
9898
.name = "bi_tcxo",
9999
},
100100
.num_parents = 1,
101-
.ops = &clk_trion_fixed_pll_ops,
101+
.ops = &clk_alpha_pll_fixed_trion_ops,
102102
},
103103
},
104104
};
@@ -118,7 +118,7 @@ static struct clk_alpha_pll gpll9 = {
118118
.name = "bi_tcxo",
119119
},
120120
.num_parents = 1,
121-
.ops = &clk_trion_fixed_pll_ops,
121+
.ops = &clk_alpha_pll_fixed_trion_ops,
122122
},
123123
},
124124
};

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