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Merge tag 'arm-soc/for-6.4/devicetree' of https://github.com/Broadcom/stblinux into soc/dt
This pull request contains Broadcom ARM-based SoCs Device Tree changes for 6.4, please pull the following: - William adds the new-style High Speed SPI controller node to the BCA SoCs * tag 'arm-soc/for-6.4/devicetree' of https://github.com/Broadcom/stblinux: ARM: dts: broadcom: bcmbca: Add spi controller node Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2 parents 325ae15 + 7858dde commit 0b3751d

17 files changed

+184
-0
lines changed

‎arch/arm/boot/dts/bcm47622.dtsi

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,12 @@
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clock-div = <4>;
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clock-mult = <1>;
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};
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hsspi_pll: hsspi-pll {
93+
compatible = "fixed-clock";
94+
#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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};
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9399
psci {
@@ -119,6 +125,18 @@
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#size-cells = <1>;
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ranges = <0 0xff800000 0x800000>;
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hsspi: spi@1000 {
129+
#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,bcm47622-hsspi", "brcm,bcmbca-hsspi-v1.0";
132+
reg = <0x1000 0x600>;
133+
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&hsspi_pll &hsspi_pll>;
135+
clock-names = "hsspi", "pll";
136+
num-cs = <8>;
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status = "disabled";
138+
};
139+
122140
uart0: serial@12000 {
123141
compatible = "arm,pl011", "arm,primecell";
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reg = <0x12000 0x1000>;

‎arch/arm/boot/dts/bcm63138.dtsi

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Original file line numberDiff line numberDiff line change
@@ -66,6 +66,12 @@
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clock-div = <4>;
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clock-mult = <1>;
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};
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hsspi_pll: hsspi-pll {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <400000000>;
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};
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};
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/* ARM bus */
@@ -203,6 +209,18 @@
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status = "disabled";
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};
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hsspi: spi@1000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,bcm63138-hsspi", "brcm,bcmbca-hsspi-v1.0";
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reg = <0x1000 0x600>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&hsspi_pll &hsspi_pll>;
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clock-names = "hsspi", "pll";
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num-cs = <8>;
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status = "disabled";
222+
};
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206224
nand_controller: nand-controller@2000 {
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#address-cells = <1>;
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#size-cells = <0>;

‎arch/arm/boot/dts/bcm63148.dtsi

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,12 @@
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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};
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hsspi_pll: hsspi-pll {
65+
compatible = "fixed-clock";
66+
#clock-cells = <0>;
67+
clock-frequency = <400000000>;
68+
};
6369
};
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psci {
@@ -100,5 +106,17 @@
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clock-names = "refclk";
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status = "disabled";
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};
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hsspi: spi@1000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,bcm63148-hsspi", "brcm,bcmbca-hsspi-v1.0";
114+
reg = <0x1000 0x600>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&hsspi_pll &hsspi_pll>;
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clock-names = "hsspi", "pll";
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num-cs = <8>;
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status = "disabled";
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};
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};
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};

‎arch/arm/boot/dts/bcm63178.dtsi

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -71,13 +71,20 @@
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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uart_clk: uart-clk {
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compatible = "fixed-factor-clock";
7677
#clock-cells = <0>;
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clocks = <&periph_clk>;
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clock-div = <4>;
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clock-mult = <1>;
8081
};
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hsspi_pll: hsspi-pll {
84+
compatible = "fixed-clock";
85+
#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
8188
};
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psci {
@@ -109,6 +116,18 @@
109116
#size-cells = <1>;
110117
ranges = <0 0xff800000 0x800000>;
111118

119+
hsspi: spi@1000 {
120+
#address-cells = <1>;
121+
#size-cells = <0>;
122+
compatible = "brcm,bcm63178-hsspi", "brcm,bcmbca-hsspi-v1.0";
123+
reg = <0x1000 0x600>;
124+
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
125+
clocks = <&hsspi_pll &hsspi_pll>;
126+
clock-names = "hsspi", "pll";
127+
num-cs = <8>;
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status = "disabled";
129+
};
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112131
uart0: serial@12000 {
113132
compatible = "arm,pl011", "arm,primecell";
114133
reg = <0x12000 0x1000>;

‎arch/arm/boot/dts/bcm6756.dtsi

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Original file line numberDiff line numberDiff line change
@@ -88,6 +88,12 @@
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clock-div = <4>;
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clock-mult = <1>;
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};
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hsspi_pll: hsspi-pll {
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compatible = "fixed-clock";
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#clock-cells = <0>;
95+
clock-frequency = <200000000>;
96+
};
9197
};
9298

9399
psci {
@@ -119,6 +125,19 @@
119125
#size-cells = <1>;
120126
ranges = <0 0xff800000 0x800000>;
121127

128+
hsspi: spi@1000 {
129+
#address-cells = <1>;
130+
#size-cells = <0>;
131+
compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1";
132+
reg = <0x1000 0x600>, <0x2610 0x4>;
133+
reg-names = "hsspi", "spim-ctrl";
134+
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
135+
clocks = <&hsspi_pll &hsspi_pll>;
136+
clock-names = "hsspi", "pll";
137+
num-cs = <8>;
138+
status = "disabled";
139+
};
140+
122141
uart0: serial@12000 {
123142
compatible = "arm,pl011", "arm,primecell";
124143
reg = <0x12000 0x1000>;

‎arch/arm/boot/dts/bcm6846.dtsi

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@@ -61,6 +61,12 @@
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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hsspi_pll: hsspi-pll {
66+
compatible = "fixed-clock";
67+
#clock-cells = <0>;
68+
clock-frequency = <400000000>;
69+
};
6470
};
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6672
psci {
@@ -100,5 +106,17 @@
100106
clock-names = "refclk";
101107
status = "disabled";
102108
};
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hsspi: spi@1000 {
111+
#address-cells = <1>;
112+
#size-cells = <0>;
113+
compatible = "brcm,bcm6846-hsspi", "brcm,bcmbca-hsspi-v1.0";
114+
reg = <0x1000 0x600>;
115+
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
116+
clocks = <&hsspi_pll &hsspi_pll>;
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clock-names = "hsspi", "pll";
118+
num-cs = <8>;
119+
status = "disabled";
120+
};
103121
};
104122
};

‎arch/arm/boot/dts/bcm6855.dtsi

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@@ -78,6 +78,12 @@
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clock-div = <4>;
7979
clock-mult = <1>;
8080
};
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hsspi_pll: hsspi-pll {
83+
compatible = "fixed-clock";
84+
#clock-cells = <0>;
85+
clock-frequency = <200000000>;
86+
};
8187
};
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8389
psci {
@@ -109,6 +115,19 @@
109115
#size-cells = <1>;
110116
ranges = <0 0xff800000 0x800000>;
111117

118+
hsspi: spi@1000 {
119+
#address-cells = <1>;
120+
#size-cells = <0>;
121+
compatible = "brcm,bcm6855-hsspi", "brcm,bcmbca-hsspi-v1.1";
122+
reg = <0x1000 0x600>, <0x2610 0x4>;
123+
reg-names = "hsspi", "spim-ctrl";
124+
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
125+
clocks = <&hsspi_pll &hsspi_pll>;
126+
clock-names = "hsspi", "pll";
127+
num-cs = <8>;
128+
status = "disabled";
129+
};
130+
112131
uart0: serial@12000 {
113132
compatible = "arm,pl011", "arm,primecell";
114133
reg = <0x12000 0x1000>;

‎arch/arm/boot/dts/bcm6878.dtsi

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@@ -61,13 +61,20 @@
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#clock-cells = <0>;
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clock-frequency = <200000000>;
6363
};
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6465
uart_clk: uart-clk {
6566
compatible = "fixed-factor-clock";
6667
#clock-cells = <0>;
6768
clocks = <&periph_clk>;
6869
clock-div = <4>;
6970
clock-mult = <1>;
7071
};
72+
73+
hsspi_pll: hsspi-pll {
74+
compatible = "fixed-clock";
75+
#clock-cells = <0>;
76+
clock-frequency = <200000000>;
77+
};
7178
};
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7380
psci {
@@ -100,6 +107,18 @@
100107
#size-cells = <1>;
101108
ranges = <0 0xff800000 0x800000>;
102109

110+
hsspi: spi@1000 {
111+
#address-cells = <1>;
112+
#size-cells = <0>;
113+
compatible = "brcm,bcm6878-hsspi", "brcm,bcmbca-hsspi-v1.0";
114+
reg = <0x1000 0x600>;
115+
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
116+
clocks = <&hsspi_pll &hsspi_pll>;
117+
clock-names = "hsspi", "pll";
118+
num-cs = <8>;
119+
status = "disabled";
120+
};
121+
103122
uart0: serial@12000 {
104123
compatible = "arm,pl011", "arm,primecell";
105124
reg = <0x12000 0x1000>;

‎arch/arm/boot/dts/bcm947622.dts

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Original file line numberDiff line numberDiff line change
@@ -28,3 +28,7 @@
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&uart0 {
2929
status = "okay";
3030
};
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&hsspi {
33+
status = "okay";
34+
};

‎arch/arm/boot/dts/bcm963138.dts

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@@ -25,3 +25,7 @@
2525
&serial0 {
2626
status = "okay";
2727
};
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&hsspi {
30+
status = "okay";
31+
};

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