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clk: mediatek: Add drivers for MT6735 syscon clock and reset controllers
Add drivers for IMGSYS, MFGCFG, VDECSYS and VENCSYS clocks and resets on MT6735. Signed-off-by: Yassine Oudjana <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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‎MAINTAINERS‎

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@@ -14534,9 +14534,13 @@ L: [email protected]
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L: [email protected] (moderated for non-subscribers)
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S: Maintained
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F: drivers/clk/mediatek/clk-mt6735-apmixedsys.c
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F: drivers/clk/mediatek/clk-mt6735-imgsys.c
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F: drivers/clk/mediatek/clk-mt6735-infracfg.c
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F: drivers/clk/mediatek/clk-mt6735-mfgcfg.c
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F: drivers/clk/mediatek/clk-mt6735-pericfg.c
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F: drivers/clk/mediatek/clk-mt6735-topckgen.c
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F: drivers/clk/mediatek/clk-mt6735-vdecsys.c
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F: drivers/clk/mediatek/clk-mt6735-vencsys.c
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F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
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F: include/dt-bindings/clock/mediatek,mt6735-imgsys.h
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F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h

‎drivers/clk/mediatek/Kconfig‎

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@@ -133,6 +133,34 @@ config COMMON_CLK_MT6735
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by apmixedsys, topckgen, infracfg and pericfg on the
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MediaTek MT6735 SoC.
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config COMMON_CLK_MT6735_IMGSYS
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tristate "Clock driver for MediaTek MT6735 imgsys"
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depends on COMMON_CLK_MT6735
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help
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This enables a driver for clocks provided by imgsys
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on the MediaTek MT6735 SoC.
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config COMMON_CLK_MT6735_MFGCFG
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tristate "Clock driver for MediaTek MT6735 mfgcfg"
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depends on COMMON_CLK_MT6735
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help
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This enables a driver for clocks and resets provided
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by mfgcfg on the MediaTek MT6735 SoC.
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config COMMON_CLK_MT6735_VDECSYS
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tristate "Clock driver for MediaTek MT6735 vdecsys"
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depends on COMMON_CLK_MT6735
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help
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This enables a driver for clocks and resets provided
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by vdecsys on the MediaTek MT6735 SoC.
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config COMMON_CLK_MT6735_VENCSYS
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tristate "Clock driver for MediaTek MT6735 vencsys"
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depends on COMMON_CLK_MT6735
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help
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This enables a driver for clocks provided by vencsys
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on the MediaTek MT6735 SoC.
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config COMMON_CLK_MT6765
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bool "Clock driver for MediaTek MT6765"
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depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST

‎drivers/clk/mediatek/Makefile‎

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@@ -3,6 +3,10 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.
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obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
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obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o
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obj-$(CONFIG_COMMON_CLK_MT6735_IMGSYS) += clk-mt6735-imgsys.o
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obj-$(CONFIG_COMMON_CLK_MT6735_MFGCFG) += clk-mt6735-mfgcfg.o
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obj-$(CONFIG_COMMON_CLK_MT6735_VDECSYS) += clk-mt6735-vdecsys.o
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obj-$(CONFIG_COMMON_CLK_MT6735_VENCSYS) += clk-mt6735-vencsys.o
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obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
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obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
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obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o

‎drivers/clk/mediatek/clk-mt6735-imgsys.c‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 Yassine Oudjana <[email protected]>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include <dt-bindings/clock/mediatek,mt6735-imgsys.h>
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#define IMG_CG_CON 0x00
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#define IMG_CG_SET 0x04
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#define IMG_CG_CLR 0x08
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static struct mtk_gate_regs imgsys_cg_regs = {
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.set_ofs = IMG_CG_SET,
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.clr_ofs = IMG_CG_CLR,
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.sta_ofs = IMG_CG_CON,
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};
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static const struct mtk_gate imgsys_gates[] = {
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GATE_MTK(CLK_IMG_SMI_LARB2, "smi_larb2", "mm_sel", &imgsys_cg_regs, 0, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_IMG_CAM_SMI, "cam_smi", "mm_sel", &imgsys_cg_regs, 5, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_IMG_CAM_CAM, "cam_cam", "mm_sel", &imgsys_cg_regs, 6, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_IMG_SEN_TG, "sen_tg", "mm_sel", &imgsys_cg_regs, 7, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_IMG_SEN_CAM, "sen_cam", "mm_sel", &imgsys_cg_regs, 8, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_IMG_CAM_SV, "cam_sv", "mm_sel", &imgsys_cg_regs, 9, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_IMG_SUFOD, "sufod", "mm_sel", &imgsys_cg_regs, 10, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_IMG_FD, "fd", "mm_sel", &imgsys_cg_regs, 11, &mtk_clk_gate_ops_setclr),
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};
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static const struct mtk_clk_desc imgsys_clks = {
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.clks = imgsys_gates,
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.num_clks = ARRAY_SIZE(imgsys_gates),
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};
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static const struct of_device_id of_match_mt6735_imgsys[] = {
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{ .compatible = "mediatek,mt6735-imgsys", .data = &imgsys_clks },
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{ /* sentinel */ }
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};
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static struct platform_driver clk_mt6735_imgsys = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt6735-imgsys",
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.of_match_table = of_match_mt6735_imgsys,
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},
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};
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module_platform_driver(clk_mt6735_imgsys);
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MODULE_AUTHOR("Yassine Oudjana <[email protected]>");
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MODULE_DESCRIPTION("MediaTek MT6735 imgsys clock driver");
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MODULE_LICENSE("GPL");

‎drivers/clk/mediatek/clk-mt6735-mfgcfg.c‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 Yassine Oudjana <[email protected]>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include <dt-bindings/clock/mediatek,mt6735-mfgcfg.h>
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#define MFG_CG_CON 0x00
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#define MFG_CG_SET 0x04
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#define MFG_CG_CLR 0x08
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#define MFG_RESET 0x0c
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static struct mtk_gate_regs mfgcfg_cg_regs = {
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.set_ofs = MFG_CG_SET,
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.clr_ofs = MFG_CG_CLR,
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.sta_ofs = MFG_CG_CON,
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};
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static const struct mtk_gate mfgcfg_gates[] = {
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GATE_MTK(CLK_MFG_BG3D, "bg3d", "mfg_sel", &mfgcfg_cg_regs, 0, &mtk_clk_gate_ops_setclr),
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};
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static u16 mfgcfg_rst_ofs[] = { MFG_RESET };
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static const struct mtk_clk_rst_desc mfgcfg_resets = {
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.version = MTK_RST_SIMPLE,
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.rst_bank_ofs = mfgcfg_rst_ofs,
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.rst_bank_nr = ARRAY_SIZE(mfgcfg_rst_ofs)
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};
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static const struct mtk_clk_desc mfgcfg_clks = {
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.clks = mfgcfg_gates,
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.num_clks = ARRAY_SIZE(mfgcfg_gates),
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.rst_desc = &mfgcfg_resets
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};
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static const struct of_device_id of_match_mt6735_mfgcfg[] = {
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{ .compatible = "mediatek,mt6735-mfgcfg", .data = &mfgcfg_clks },
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{ /* sentinel */ }
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};
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static struct platform_driver clk_mt6735_mfgcfg = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt6735-mfgcfg",
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.of_match_table = of_match_mt6735_mfgcfg,
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},
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};
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module_platform_driver(clk_mt6735_mfgcfg);
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MODULE_AUTHOR("Yassine Oudjana <[email protected]>");
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MODULE_DESCRIPTION("Mediatek MT6735 mfgcfg clock and reset driver");
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MODULE_LICENSE("GPL");

‎drivers/clk/mediatek/clk-mt6735-vdecsys.c‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 Yassine Oudjana <[email protected]>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include <dt-bindings/clock/mediatek,mt6735-vdecsys.h>
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#include <dt-bindings/reset/mediatek,mt6735-vdecsys.h>
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#define VDEC_CKEN_SET 0x00
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#define VDEC_CKEN_CLR 0x04
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#define SMI_LARB1_CKEN_SET 0x08
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#define SMI_LARB1_CKEN_CLR 0x0c
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#define VDEC_RESETB_CON 0x10
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#define SMI_LARB1_RESETB_CON 0x14
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#define RST_NR_PER_BANK 32
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static struct mtk_gate_regs vdec_cg_regs = {
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.set_ofs = VDEC_CKEN_SET,
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.clr_ofs = VDEC_CKEN_CLR,
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.sta_ofs = VDEC_CKEN_SET,
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};
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static struct mtk_gate_regs smi_larb1_cg_regs = {
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.set_ofs = SMI_LARB1_CKEN_SET,
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.clr_ofs = SMI_LARB1_CKEN_CLR,
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.sta_ofs = SMI_LARB1_CKEN_SET,
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};
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static const struct mtk_gate vdecsys_gates[] = {
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GATE_MTK(CLK_VDEC_VDEC, "vdec", "vdec_sel", &vdec_cg_regs, 0, &mtk_clk_gate_ops_setclr_inv),
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GATE_MTK(CLK_VDEC_SMI_LARB1, "smi_larb1", "vdec_sel", &smi_larb1_cg_regs, 0, &mtk_clk_gate_ops_setclr_inv),
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};
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static u16 vdecsys_rst_bank_ofs[] = { VDEC_RESETB_CON, SMI_LARB1_RESETB_CON };
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static u16 vdecsys_rst_idx_map[] = {
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[MT6735_VDEC_RST0_VDEC] = 0 * RST_NR_PER_BANK + 0,
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[MT6735_VDEC_RST1_SMI_LARB1] = 1 * RST_NR_PER_BANK + 0,
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};
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static const struct mtk_clk_rst_desc vdecsys_resets = {
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.version = MTK_RST_SIMPLE,
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.rst_bank_ofs = vdecsys_rst_bank_ofs,
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.rst_bank_nr = ARRAY_SIZE(vdecsys_rst_bank_ofs),
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.rst_idx_map = vdecsys_rst_idx_map,
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.rst_idx_map_nr = ARRAY_SIZE(vdecsys_rst_idx_map)
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};
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static const struct mtk_clk_desc vdecsys_clks = {
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.clks = vdecsys_gates,
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.num_clks = ARRAY_SIZE(vdecsys_gates),
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.rst_desc = &vdecsys_resets
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};
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static const struct of_device_id of_match_mt6735_vdecsys[] = {
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{ .compatible = "mediatek,mt6735-vdecsys", .data = &vdecsys_clks },
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{ /* sentinel */ }
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};
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static struct platform_driver clk_mt6735_vdecsys = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt6735-vdecsys",
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.of_match_table = of_match_mt6735_vdecsys,
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},
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};
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module_platform_driver(clk_mt6735_vdecsys);
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MODULE_AUTHOR("Yassine Oudjana <[email protected]>");
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MODULE_DESCRIPTION("MediaTek MT6735 vdecsys clock and reset driver");
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MODULE_LICENSE("GPL");

‎drivers/clk/mediatek/clk-mt6735-vencsys.c‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 Yassine Oudjana <[email protected]>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include <dt-bindings/clock/mediatek,mt6735-vencsys.h>
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#define VENC_CG_CON 0x00
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#define VENC_CG_SET 0x04
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#define VENC_CG_CLR 0x08
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static struct mtk_gate_regs venc_cg_regs = {
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.set_ofs = VENC_CG_SET,
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.clr_ofs = VENC_CG_CLR,
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.sta_ofs = VENC_CG_CON,
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};
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static const struct mtk_gate vencsys_gates[] = {
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GATE_MTK(CLK_VENC_SMI_LARB3, "smi_larb3", "mm_sel", &venc_cg_regs, 0, &mtk_clk_gate_ops_setclr_inv),
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GATE_MTK(CLK_VENC_VENC, "venc", "mm_sel", &venc_cg_regs, 4, &mtk_clk_gate_ops_setclr_inv),
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GATE_MTK(CLK_VENC_JPGENC, "jpgenc", "mm_sel", &venc_cg_regs, 8, &mtk_clk_gate_ops_setclr_inv),
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GATE_MTK(CLK_VENC_JPGDEC, "jpgdec", "mm_sel", &venc_cg_regs, 12, &mtk_clk_gate_ops_setclr_inv),
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};
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static const struct mtk_clk_desc vencsys_clks = {
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.clks = vencsys_gates,
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.num_clks = ARRAY_SIZE(vencsys_gates),
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};
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static const struct of_device_id of_match_mt6735_vencsys[] = {
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{ .compatible = "mediatek,mt6735-vencsys", .data = &vencsys_clks },
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{ /* sentinel */ }
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};
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static struct platform_driver clk_mt6735_vencsys = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt6735-vencsys",
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.of_match_table = of_match_mt6735_vencsys,
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},
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};
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module_platform_driver(clk_mt6735_vencsys);
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MODULE_AUTHOR("Yassine Oudjana <[email protected]>");
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MODULE_DESCRIPTION("Mediatek MT6735 vencsys clock driver");
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MODULE_LICENSE("GPL");

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