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Md Sadre Alammiquelraynal
Md Sadre Alam
authored and
miquelraynal
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mtd: rawnand: qcom: use FIELD_PREP and GENMASK
Use the bitfield macro FIELD_PREP, and GENMASK to do the shift and mask in one go. This makes the code more readable. Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Md Sadre Alam <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
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-61
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2 files changed

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‎drivers/mtd/nand/raw/qcom_nandc.c

Lines changed: 48 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -281,7 +281,7 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, i
281281
(num_cw - 1) << CW_PER_PAGE);
282282

283283
cfg1 = cpu_to_le32(host->cfg1_raw);
284-
ecc_bch_cfg = cpu_to_le32(1 << ECC_CFG_ECC_DISABLE);
284+
ecc_bch_cfg = cpu_to_le32(ECC_CFG_ECC_DISABLE);
285285
}
286286

287287
nandc->regs->cmd = cmd;
@@ -1494,42 +1494,41 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
14941494
host->cw_size = host->cw_data + ecc->bytes;
14951495
bad_block_byte = mtd->writesize - host->cw_size * (cwperpage - 1) + 1;
14961496

1497-
host->cfg0 = (cwperpage - 1) << CW_PER_PAGE
1498-
| host->cw_data << UD_SIZE_BYTES
1499-
| 0 << DISABLE_STATUS_AFTER_WRITE
1500-
| 5 << NUM_ADDR_CYCLES
1501-
| host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_RS
1502-
| 0 << STATUS_BFR_READ
1503-
| 1 << SET_RD_MODE_AFTER_STATUS
1504-
| host->spare_bytes << SPARE_SIZE_BYTES;
1505-
1506-
host->cfg1 = 7 << NAND_RECOVERY_CYCLES
1507-
| 0 << CS_ACTIVE_BSY
1508-
| bad_block_byte << BAD_BLOCK_BYTE_NUM
1509-
| 0 << BAD_BLOCK_IN_SPARE_AREA
1510-
| 2 << WR_RD_BSY_GAP
1511-
| wide_bus << WIDE_FLASH
1512-
| host->bch_enabled << ENABLE_BCH_ECC;
1513-
1514-
host->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE
1515-
| host->cw_size << UD_SIZE_BYTES
1516-
| 5 << NUM_ADDR_CYCLES
1517-
| 0 << SPARE_SIZE_BYTES;
1518-
1519-
host->cfg1_raw = 7 << NAND_RECOVERY_CYCLES
1520-
| 0 << CS_ACTIVE_BSY
1521-
| 17 << BAD_BLOCK_BYTE_NUM
1522-
| 1 << BAD_BLOCK_IN_SPARE_AREA
1523-
| 2 << WR_RD_BSY_GAP
1524-
| wide_bus << WIDE_FLASH
1525-
| 1 << DEV0_CFG1_ECC_DISABLE;
1526-
1527-
host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
1528-
| 0 << ECC_SW_RESET
1529-
| host->cw_data << ECC_NUM_DATA_BYTES
1530-
| 1 << ECC_FORCE_CLK_OPEN
1531-
| ecc_mode << ECC_MODE
1532-
| host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
1497+
host->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
1498+
FIELD_PREP(UD_SIZE_BYTES_MASK, host->cw_data) |
1499+
FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 0) |
1500+
FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) |
1501+
FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, host->ecc_bytes_hw) |
1502+
FIELD_PREP(STATUS_BFR_READ, 0) |
1503+
FIELD_PREP(SET_RD_MODE_AFTER_STATUS, 1) |
1504+
FIELD_PREP(SPARE_SIZE_BYTES_MASK, host->spare_bytes);
1505+
1506+
host->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) |
1507+
FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, bad_block_byte) |
1508+
FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 0) |
1509+
FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) |
1510+
FIELD_PREP(WIDE_FLASH, wide_bus) |
1511+
FIELD_PREP(ENABLE_BCH_ECC, host->bch_enabled);
1512+
1513+
host->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
1514+
FIELD_PREP(UD_SIZE_BYTES_MASK, host->cw_size) |
1515+
FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) |
1516+
FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
1517+
1518+
host->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) |
1519+
FIELD_PREP(CS_ACTIVE_BSY, 0) |
1520+
FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
1521+
FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
1522+
FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) |
1523+
FIELD_PREP(WIDE_FLASH, wide_bus) |
1524+
FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
1525+
1526+
host->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !host->bch_enabled) |
1527+
FIELD_PREP(ECC_SW_RESET, 0) |
1528+
FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, host->cw_data) |
1529+
FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
1530+
FIELD_PREP(ECC_MODE_MASK, ecc_mode) |
1531+
FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, host->ecc_bytes_hw);
15331532

15341533
if (!nandc->props->qpic_version2)
15351534
host->ecc_buf_cfg = 0x203 << NUM_STEPS;
@@ -1882,21 +1881,21 @@ static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_
18821881
nandc->regs->addr0 = 0;
18831882
nandc->regs->addr1 = 0;
18841883

1885-
nandc->regs->cfg0 = cpu_to_le32(0 << CW_PER_PAGE |
1886-
512 << UD_SIZE_BYTES |
1887-
5 << NUM_ADDR_CYCLES |
1888-
0 << SPARE_SIZE_BYTES);
1884+
host->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, 0) |
1885+
FIELD_PREP(UD_SIZE_BYTES_MASK, 512) |
1886+
FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) |
1887+
FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
18891888

1890-
nandc->regs->cfg1 = cpu_to_le32(7 << NAND_RECOVERY_CYCLES |
1891-
0 << CS_ACTIVE_BSY |
1892-
17 << BAD_BLOCK_BYTE_NUM |
1893-
1 << BAD_BLOCK_IN_SPARE_AREA |
1894-
2 << WR_RD_BSY_GAP |
1895-
0 << WIDE_FLASH |
1896-
1 << DEV0_CFG1_ECC_DISABLE);
1889+
host->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) |
1890+
FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
1891+
FIELD_PREP(CS_ACTIVE_BSY, 0) |
1892+
FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
1893+
FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) |
1894+
FIELD_PREP(WIDE_FLASH, 0) |
1895+
FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
18971896

18981897
if (!nandc->props->qpic_version2)
1899-
nandc->regs->ecc_buf_cfg = cpu_to_le32(1 << ECC_CFG_ECC_DISABLE);
1898+
nandc->regs->ecc_buf_cfg = cpu_to_le32(ECC_CFG_ECC_DISABLE);
19001899

19011900
/* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
19021901
if (!nandc->props->qpic_version2) {

‎include/linux/mtd/nand-qpic-common.h

Lines changed: 19 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -70,35 +70,42 @@
7070
#define BS_CORRECTABLE_ERR_MSK 0x1f
7171

7272
/* NAND_DEVn_CFG0 bits */
73-
#define DISABLE_STATUS_AFTER_WRITE 4
73+
#define DISABLE_STATUS_AFTER_WRITE BIT(4)
7474
#define CW_PER_PAGE 6
75+
#define CW_PER_PAGE_MASK GENMASK(8, 6)
7576
#define UD_SIZE_BYTES 9
7677
#define UD_SIZE_BYTES_MASK GENMASK(18, 9)
77-
#define ECC_PARITY_SIZE_BYTES_RS 19
78+
#define ECC_PARITY_SIZE_BYTES_RS GENMASK(22, 19)
7879
#define SPARE_SIZE_BYTES 23
7980
#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23)
8081
#define NUM_ADDR_CYCLES 27
81-
#define STATUS_BFR_READ 30
82-
#define SET_RD_MODE_AFTER_STATUS 31
82+
#define NUM_ADDR_CYCLES_MASK GENMASK(29, 27)
83+
#define STATUS_BFR_READ BIT(30)
84+
#define SET_RD_MODE_AFTER_STATUS BIT(31)
8385

8486
/* NAND_DEVn_CFG0 bits */
85-
#define DEV0_CFG1_ECC_DISABLE 0
86-
#define WIDE_FLASH 1
87+
#define DEV0_CFG1_ECC_DISABLE BIT(0)
88+
#define WIDE_FLASH BIT(1)
8789
#define NAND_RECOVERY_CYCLES 2
88-
#define CS_ACTIVE_BSY 5
90+
#define NAND_RECOVERY_CYCLES_MASK GENMASK(4, 2)
91+
#define CS_ACTIVE_BSY BIT(5)
8992
#define BAD_BLOCK_BYTE_NUM 6
90-
#define BAD_BLOCK_IN_SPARE_AREA 16
93+
#define BAD_BLOCK_BYTE_NUM_MASK GENMASK(15, 6)
94+
#define BAD_BLOCK_IN_SPARE_AREA BIT(16)
9195
#define WR_RD_BSY_GAP 17
92-
#define ENABLE_BCH_ECC 27
96+
#define WR_RD_BSY_GAP_MASK GENMASK(22, 17)
97+
#define ENABLE_BCH_ECC BIT(27)
9398

9499
/* NAND_DEV0_ECC_CFG bits */
95-
#define ECC_CFG_ECC_DISABLE 0
96-
#define ECC_SW_RESET 1
100+
#define ECC_CFG_ECC_DISABLE BIT(0)
101+
#define ECC_SW_RESET BIT(1)
97102
#define ECC_MODE 4
103+
#define ECC_MODE_MASK GENMASK(5, 4)
98104
#define ECC_PARITY_SIZE_BYTES_BCH 8
105+
#define ECC_PARITY_SIZE_BYTES_BCH_MASK GENMASK(12, 8)
99106
#define ECC_NUM_DATA_BYTES 16
100107
#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16)
101-
#define ECC_FORCE_CLK_OPEN 30
108+
#define ECC_FORCE_CLK_OPEN BIT(30)
102109

103110
/* NAND_DEV_CMD1 bits */
104111
#define READ_ADDR 0

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