Skip to content

Commit 0c983d3

Browse files
robherringMani-Sadhasivam
robherring
authored and
Mani-Sadhasivam
committed
dt-bindings: PCI: Convert Marvell EBU to schema
Convert the Marvell EBU (Kirkwood, Dove, Armada XP/370) to DT schema format. Add "error" to interrupt-names which is in use, but missing. Shorten the example from 10 child nodes to 6 as the additional ones don't add much value to the example. Signed-off-by: Rob Herring (Arm) <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://patch.msgid.link/[email protected]
1 parent 39813e1 commit 0c983d3

File tree

2 files changed

+277
-310
lines changed

2 files changed

+277
-310
lines changed

‎Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml

Lines changed: 277 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,277 @@
1+
# SPDX-License-Identifier: GPL-2.0
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/pci/marvell,kirkwood-pcie.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Marvell EBU PCIe interfaces
8+
9+
maintainers:
10+
- Thomas Petazzoni <[email protected]>
11+
- Pali Rohár <[email protected]>
12+
13+
allOf:
14+
- $ref: /schemas/pci/pci-host-bridge.yaml#
15+
16+
properties:
17+
compatible:
18+
enum:
19+
- marvell,armada-370-pcie
20+
- marvell,armada-xp-pcie
21+
- marvell,dove-pcie
22+
- marvell,kirkwood-pcie
23+
24+
ranges:
25+
description: >
26+
The ranges describing the MMIO registers have the following layout:
27+
28+
0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
29+
30+
where:
31+
32+
* r is a 32-bits value that gives the offset of the MMIO registers of
33+
this PCIe interface, from the base of the internal registers.
34+
35+
* s is a 32-bits value that give the size of this MMIO registers area.
36+
This range entry translates the '0x82000000 0 r' PCI address into the
37+
'MBUS_ID(0xf0, 0x01) r' CPU address, which is part of the internal
38+
register window (as identified by MBUS_ID(0xf0, 0x01)).
39+
40+
The ranges describing the MBus windows have the following layout:
41+
42+
0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
43+
44+
where:
45+
46+
* t is the type of the MBus window (as defined by the standard PCI DT
47+
bindings), 1 for I/O and 2 for memory.
48+
49+
* s is the PCI slot that corresponds to this PCIe interface
50+
51+
* w is the 'target ID' value for the MBus window
52+
53+
* a the 'attribute' value for the MBus window.
54+
55+
Since the location and size of the different MBus windows is not fixed in
56+
hardware, and only determined in runtime, those ranges cover the full first
57+
4 GB of the physical address space, and do not translate into a valid CPU
58+
address.
59+
60+
msi-parent:
61+
maxItems: 1
62+
63+
patternProperties:
64+
'^pcie@':
65+
type: object
66+
allOf:
67+
- $ref: /schemas/pci/pci-bus-common.yaml#
68+
- $ref: /schemas/pci/pci-device.yaml#
69+
unevaluatedProperties: false
70+
71+
properties:
72+
clocks:
73+
maxItems: 1
74+
75+
interrupts:
76+
minItems: 1
77+
maxItems: 2
78+
79+
interrupt-names:
80+
minItems: 1
81+
items:
82+
- const: intx
83+
- const: error
84+
85+
reset-delay-us:
86+
default: 100000
87+
description: todo
88+
89+
marvell,pcie-port:
90+
$ref: /schemas/types.yaml#/definitions/uint32
91+
maximum: 3
92+
description: todo
93+
94+
marvell,pcie-lane:
95+
$ref: /schemas/types.yaml#/definitions/uint32
96+
maximum: 3
97+
description: todo
98+
99+
interrupt-controller:
100+
type: object
101+
additionalProperties: false
102+
103+
properties:
104+
interrupt-controller: true
105+
106+
'#interrupt-cells':
107+
const: 1
108+
109+
required:
110+
- assigned-addresses
111+
- clocks
112+
- interrupt-map
113+
- marvell,pcie-port
114+
115+
unevaluatedProperties: false
116+
117+
examples:
118+
- |
119+
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
120+
121+
soc {
122+
#address-cells = <2>;
123+
#size-cells = <2>;
124+
125+
pcie@f001000000000000 {
126+
compatible = "marvell,armada-xp-pcie";
127+
device_type = "pci";
128+
129+
#address-cells = <3>;
130+
#size-cells = <2>;
131+
132+
bus-range = <0x00 0xff>;
133+
msi-parent = <&mpic>;
134+
135+
ranges =
136+
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
137+
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
138+
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
139+
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
140+
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
141+
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
142+
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
143+
0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
144+
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
145+
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
146+
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
147+
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
148+
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
149+
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
150+
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
151+
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
152+
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
153+
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
154+
155+
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
156+
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
157+
0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
158+
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
159+
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
160+
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
161+
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
162+
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
163+
164+
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
165+
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
166+
167+
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
168+
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
169+
170+
pcie@1,0 {
171+
device_type = "pci";
172+
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
173+
reg = <0x0800 0 0 0 0>;
174+
#address-cells = <3>;
175+
#size-cells = <2>;
176+
#interrupt-cells = <1>;
177+
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
178+
0x81000000 0 0 0x81000000 0x1 0 1 0>;
179+
interrupt-map-mask = <0 0 0 0>;
180+
interrupt-map = <0 0 0 0 &mpic 58>;
181+
marvell,pcie-port = <0>;
182+
marvell,pcie-lane = <0>;
183+
num-lanes = <1>;
184+
/* low-active PERST# reset on GPIO 25 */
185+
reset-gpios = <&gpio0 25 1>;
186+
/* wait 20ms for device settle after reset deassertion */
187+
reset-delay-us = <20000>;
188+
clocks = <&gateclk 5>;
189+
};
190+
191+
pcie@2,0 {
192+
device_type = "pci";
193+
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
194+
reg = <0x1000 0 0 0 0>;
195+
#address-cells = <3>;
196+
#size-cells = <2>;
197+
#interrupt-cells = <1>;
198+
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
199+
0x81000000 0 0 0x81000000 0x2 0 1 0>;
200+
interrupt-map-mask = <0 0 0 0>;
201+
interrupt-map = <0 0 0 0 &mpic 59>;
202+
marvell,pcie-port = <0>;
203+
marvell,pcie-lane = <1>;
204+
num-lanes = <1>;
205+
clocks = <&gateclk 6>;
206+
};
207+
208+
pcie@3,0 {
209+
device_type = "pci";
210+
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
211+
reg = <0x1800 0 0 0 0>;
212+
#address-cells = <3>;
213+
#size-cells = <2>;
214+
#interrupt-cells = <1>;
215+
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
216+
0x81000000 0 0 0x81000000 0x3 0 1 0>;
217+
interrupt-map-mask = <0 0 0 0>;
218+
interrupt-map = <0 0 0 0 &mpic 60>;
219+
marvell,pcie-port = <0>;
220+
marvell,pcie-lane = <2>;
221+
num-lanes = <1>;
222+
clocks = <&gateclk 7>;
223+
};
224+
225+
pcie@4,0 {
226+
device_type = "pci";
227+
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
228+
reg = <0x2000 0 0 0 0>;
229+
#address-cells = <3>;
230+
#size-cells = <2>;
231+
#interrupt-cells = <1>;
232+
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
233+
0x81000000 0 0 0x81000000 0x4 0 1 0>;
234+
interrupt-map-mask = <0 0 0 0>;
235+
interrupt-map = <0 0 0 0 &mpic 61>;
236+
marvell,pcie-port = <0>;
237+
marvell,pcie-lane = <3>;
238+
num-lanes = <1>;
239+
clocks = <&gateclk 8>;
240+
};
241+
242+
pcie@5,0 {
243+
device_type = "pci";
244+
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
245+
reg = <0x2800 0 0 0 0>;
246+
#address-cells = <3>;
247+
#size-cells = <2>;
248+
#interrupt-cells = <1>;
249+
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
250+
0x81000000 0 0 0x81000000 0x5 0 1 0>;
251+
interrupt-map-mask = <0 0 0 0>;
252+
interrupt-map = <0 0 0 0 &mpic 62>;
253+
marvell,pcie-port = <1>;
254+
marvell,pcie-lane = <0>;
255+
num-lanes = <1>;
256+
clocks = <&gateclk 9>;
257+
};
258+
259+
pcie@6,0 {
260+
device_type = "pci";
261+
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
262+
reg = <0x3000 0 0 0 0>;
263+
#address-cells = <3>;
264+
#size-cells = <2>;
265+
#interrupt-cells = <1>;
266+
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
267+
0x81000000 0 0 0x81000000 0x6 0 1 0>;
268+
interrupt-map-mask = <0 0 0 0>;
269+
interrupt-map = <0 0 0 0 &mpic 63>;
270+
marvell,pcie-port = <1>;
271+
marvell,pcie-lane = <1>;
272+
num-lanes = <1>;
273+
clocks = <&gateclk 10>;
274+
};
275+
};
276+
};
277+
...

0 commit comments

Comments
 (0)