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#define QDSP6SS_MEM_PWR_CTL 0x0B0
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#define QDSP6V6SS_MEM_PWR_CTL 0x034
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#define QDSP6SS_STRAP_ACC 0x110
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+ #define QDSP6V62SS_BHS_STATUS 0x0C4
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/* AXI Halt Register Offsets */
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#define AXI_HALTREQ_REG 0x0
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#define QDSP6v56_CLAMP_QMC_MEM BIT(22)
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#define QDSP6SS_XO_CBCR 0x0038
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#define QDSP6SS_ACC_OVERRIDE_VAL 0x20
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+ #define QDSP6v55_BHS_EN_REST_ACK BIT(0)
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/* QDSP6v65 parameters */
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#define QDSP6SS_CORE_CBCR 0x20
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#define QDSP6SS_SLEEP 0x3C
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#define QDSP6SS_BOOT_CORE_START 0x400
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#define QDSP6SS_BOOT_CMD 0x404
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#define BOOT_FSM_TIMEOUT 10000
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+ #define BHS_CHECK_MAX_LOOPS 200
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struct reg_info {
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struct regulator * reg ;
@@ -250,6 +253,7 @@ enum {
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MSS_MSM8998 ,
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MSS_SC7180 ,
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MSS_SC7280 ,
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+ MSS_SDM660 ,
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MSS_SDM845 ,
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};
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@@ -700,7 +704,8 @@ static int q6v5proc_reset(struct q6v5 *qproc)
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} else if (qproc -> version == MSS_MSM8909 ||
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qproc -> version == MSS_MSM8953 ||
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qproc -> version == MSS_MSM8996 ||
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- qproc -> version == MSS_MSM8998 ) {
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+ qproc -> version == MSS_MSM8998 ||
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+ qproc -> version == MSS_SDM660 ) {
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if (qproc -> version != MSS_MSM8909 &&
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qproc -> version != MSS_MSM8953 )
@@ -734,6 +739,16 @@ static int q6v5proc_reset(struct q6v5 *qproc)
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val |= readl (qproc -> reg_base + QDSP6SS_PWR_CTL_REG );
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udelay (1 );
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+ if (qproc -> version == MSS_SDM660 ) {
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+ ret = readl_relaxed_poll_timeout (qproc -> reg_base + QDSP6V62SS_BHS_STATUS ,
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+ i , (i & QDSP6v55_BHS_EN_REST_ACK ),
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+ 1 , BHS_CHECK_MAX_LOOPS );
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+ if (ret == - ETIMEDOUT ) {
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+ dev_err (qproc -> dev , "BHS_EN_REST_ACK not set!\n" );
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+ return - ETIMEDOUT ;
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+ }
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+ }
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+
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/* Put LDO in bypass mode */
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val |= QDSP6v56_LDO_BYP ;
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writel (val , qproc -> reg_base + QDSP6SS_PWR_CTL_REG );
@@ -756,7 +771,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
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mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL ;
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i = 19 ;
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} else {
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- /* MSS_MSM8998 */
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+ /* MSS_MSM8998, MSS_SDM660 */
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mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL ;
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i = 28 ;
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}
@@ -2199,6 +2214,37 @@ static const struct rproc_hexagon_res sc7280_mss = {
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.version = MSS_SC7280 ,
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};
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+ static const struct rproc_hexagon_res sdm660_mss = {
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+ .hexagon_mba_image = "mba.mbn" ,
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+ .proxy_clk_names = (char * []){
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+ "xo" ,
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+ "qdss" ,
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+ "mem" ,
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+ NULL
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+ },
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+ .active_clk_names = (char * []){
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+ "iface" ,
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+ "bus" ,
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+ "gpll0_mss" ,
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+ "mnoc_axi" ,
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+ "snoc_axi" ,
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+ NULL
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+ },
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+ .proxy_pd_names = (char * []){
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+ "cx" ,
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+ "mx" ,
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+ NULL
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+ },
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+ .need_mem_protection = true,
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+ .has_alt_reset = false,
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+ .has_mba_logs = false,
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+ .has_spare_reg = false,
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+ .has_qaccept_regs = false,
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+ .has_ext_cntl_regs = false,
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+ .has_vq6 = false,
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+ .version = MSS_SDM660 ,
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+ };
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+
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static const struct rproc_hexagon_res sdm845_mss = {
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.hexagon_mba_image = "mba.mbn" ,
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.proxy_clk_names = (char * []){
@@ -2481,6 +2527,7 @@ static const struct of_device_id q6v5_of_match[] = {
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{ .compatible = "qcom,msm8998-mss-pil" , .data = & msm8998_mss },
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{ .compatible = "qcom,sc7180-mss-pil" , .data = & sc7180_mss },
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{ .compatible = "qcom,sc7280-mss-pil" , .data = & sc7280_mss },
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+ { .compatible = "qcom,sdm660-mss-pil" , .data = & sdm660_mss },
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{ .compatible = "qcom,sdm845-mss-pil" , .data = & sdm845_mss },
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{ },
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};
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