clk: qcom: dispcc-sdm845: Adjust internal GDSC wait times

SDM845 downstream uses non-default values for GDSC internal waits.
Program them accordingly to avoid surprises.

Fixes: 8135177 ("clk: qcom: Add display clock controller driver for SDM845")
Signed-off-by: Konrad Dybcio <[email protected]>
Tested-by: Caleb Connolly <[email protected]> # OnePlus 6
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

Author: konradybcio

drivers/clk/qcom/dispcc-sdm845.c

@@ -759,6 +759,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk = {
 
 static struct gdsc mdss_gdsc = {
 	.gdscr = 0x3000,
+	.en_few_wait_val = 0x6,
+	.en_rest_wait_val = 0x5,
 	.pd = {
 		.name = "mdss_gdsc",
 	},