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Merge tag 'drm-intel-fixes-2020-04-23' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
- Tigerlake Workaround - disabling media recompression (Matt) - Fix RPS interrupts for right GPU frequency (Chris) - HDCP fix prime check (Oliver) - Tigerlake Thunderbolt power well fix (Matt) - Tigerlake DP link training fixes (Jose) - Documentation sphinx build fix (Jani) - Fix enable_dpcd_backlight modparam (Lyude) Signed-off-by: Dave Airlie <[email protected]> From: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents c2c39ad + d082119 commit 11c5ec7

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9 files changed

+44
-23
lines changed

9 files changed

+44
-23
lines changed

‎drivers/gpu/drm/i915/display/intel_ddi.c

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3141,9 +3141,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
31413141
intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
31423142
crtc_state->lane_count, is_mst);
31433143

3144-
intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
3145-
intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
3146-
31473144
intel_edp_panel_on(intel_dp);
31483145

31493146
intel_ddi_clk_select(encoder, crtc_state);
@@ -3848,12 +3845,18 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
38483845
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
38493846
struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
38503847
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3848+
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
38513849
u32 temp, flags = 0;
38523850

38533851
/* XXX: DSI transcoder paranoia */
38543852
if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
38553853
return;
38563854

3855+
if (INTEL_GEN(dev_priv) >= 12) {
3856+
intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(cpu_transcoder);
3857+
intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(cpu_transcoder);
3858+
}
3859+
38573860
intel_dsc_get_config(encoder, pipe_config);
38583861

38593862
temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
@@ -4173,6 +4176,7 @@ static const struct drm_encoder_funcs intel_ddi_funcs = {
41734176
static struct intel_connector *
41744177
intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
41754178
{
4179+
struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
41764180
struct intel_connector *connector;
41774181
enum port port = intel_dig_port->base.port;
41784182

@@ -4183,6 +4187,10 @@ intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
41834187
intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
41844188
intel_dig_port->dp.prepare_link_retrain =
41854189
intel_ddi_prepare_link_retrain;
4190+
if (INTEL_GEN(dev_priv) < 12) {
4191+
intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
4192+
intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
4193+
}
41864194

41874195
if (!intel_dp_init_connector(intel_dig_port, connector)) {
41884196
kfree(connector);

‎drivers/gpu/drm/i915/display/intel_display_power.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4140,7 +4140,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
41404140
{
41414141
.name = "AUX D TBT1",
41424142
.domains = TGL_AUX_D_TBT1_IO_POWER_DOMAINS,
4143-
.ops = &hsw_power_well_ops,
4143+
.ops = &icl_tc_phy_aux_power_well_ops,
41444144
.id = DISP_PW_ID_NONE,
41454145
{
41464146
.hsw.regs = &icl_aux_power_well_regs,
@@ -4151,7 +4151,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
41514151
{
41524152
.name = "AUX E TBT2",
41534153
.domains = TGL_AUX_E_TBT2_IO_POWER_DOMAINS,
4154-
.ops = &hsw_power_well_ops,
4154+
.ops = &icl_tc_phy_aux_power_well_ops,
41554155
.id = DISP_PW_ID_NONE,
41564156
{
41574157
.hsw.regs = &icl_aux_power_well_regs,
@@ -4162,7 +4162,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
41624162
{
41634163
.name = "AUX F TBT3",
41644164
.domains = TGL_AUX_F_TBT3_IO_POWER_DOMAINS,
4165-
.ops = &hsw_power_well_ops,
4165+
.ops = &icl_tc_phy_aux_power_well_ops,
41664166
.id = DISP_PW_ID_NONE,
41674167
{
41684168
.hsw.regs = &icl_aux_power_well_regs,
@@ -4173,7 +4173,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
41734173
{
41744174
.name = "AUX G TBT4",
41754175
.domains = TGL_AUX_G_TBT4_IO_POWER_DOMAINS,
4176-
.ops = &hsw_power_well_ops,
4176+
.ops = &icl_tc_phy_aux_power_well_ops,
41774177
.id = DISP_PW_ID_NONE,
41784178
{
41794179
.hsw.regs = &icl_aux_power_well_regs,
@@ -4184,7 +4184,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
41844184
{
41854185
.name = "AUX H TBT5",
41864186
.domains = TGL_AUX_H_TBT5_IO_POWER_DOMAINS,
4187-
.ops = &hsw_power_well_ops,
4187+
.ops = &icl_tc_phy_aux_power_well_ops,
41884188
.id = DISP_PW_ID_NONE,
41894189
{
41904190
.hsw.regs = &icl_aux_power_well_regs,
@@ -4195,7 +4195,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
41954195
{
41964196
.name = "AUX I TBT6",
41974197
.domains = TGL_AUX_I_TBT6_IO_POWER_DOMAINS,
4198-
.ops = &hsw_power_well_ops,
4198+
.ops = &icl_tc_phy_aux_power_well_ops,
41994199
.id = DISP_PW_ID_NONE,
42004200
{
42014201
.hsw.regs = &icl_aux_power_well_regs,

‎drivers/gpu/drm/i915/display/intel_dp.c

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2517,9 +2517,6 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
25172517
intel_crtc_has_type(pipe_config,
25182518
INTEL_OUTPUT_DP_MST));
25192519

2520-
intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
2521-
intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
2522-
25232520
/*
25242521
* There are four kinds of DP registers:
25252522
*
@@ -7836,6 +7833,8 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
78367833

78377834
intel_dig_port->dp.output_reg = output_reg;
78387835
intel_dig_port->max_lanes = 4;
7836+
intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
7837+
intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
78397838

78407839
intel_encoder->type = INTEL_OUTPUT_DP;
78417840
intel_encoder->power_domain = intel_port_to_power_domain(port);

‎drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -342,6 +342,7 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector)
342342
*/
343343
if (dev_priv->vbt.backlight.type !=
344344
INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE &&
345+
i915_modparams.enable_dpcd_backlight != 1 &&
345346
!drm_dp_has_quirk(&intel_dp->desc, intel_dp->edid_quirks,
346347
DP_QUIRK_FORCE_DPCD_BACKLIGHT)) {
347348
DRM_DEV_INFO(dev->dev,

‎drivers/gpu/drm/i915/display/intel_hdmi.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1536,7 +1536,8 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
15361536
intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
15371537

15381538
/* Wait for Ri prime match */
1539-
if (wait_for(intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1539+
if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1540+
(HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
15401541
(HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
15411542
DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
15421543
intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)));

‎drivers/gpu/drm/i915/display/intel_sprite.c

Lines changed: 12 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2817,19 +2817,25 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
28172817
}
28182818
}
28192819

2820-
static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id)
2820+
static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
2821+
enum plane_id plane_id)
28212822
{
2823+
/* Wa_14010477008:tgl[a0..c0] */
2824+
if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
2825+
return false;
2826+
28222827
return plane_id < PLANE_SPRITE4;
28232828
}
28242829

28252830
static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
28262831
u32 format, u64 modifier)
28272832
{
2833+
struct drm_i915_private *dev_priv = to_i915(_plane->dev);
28282834
struct intel_plane *plane = to_intel_plane(_plane);
28292835

28302836
switch (modifier) {
28312837
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2832-
if (!gen12_plane_supports_mc_ccs(plane->id))
2838+
if (!gen12_plane_supports_mc_ccs(dev_priv, plane->id))
28332839
return false;
28342840
/* fall through */
28352841
case DRM_FORMAT_MOD_LINEAR:
@@ -2998,9 +3004,10 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
29983004
}
29993005
}
30003006

3001-
static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id)
3007+
static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
3008+
enum plane_id plane_id)
30023009
{
3003-
if (gen12_plane_supports_mc_ccs(plane_id))
3010+
if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
30043011
return gen12_plane_format_modifiers_mc_ccs;
30053012
else
30063013
return gen12_plane_format_modifiers_rc_ccs;
@@ -3070,7 +3077,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
30703077

30713078
plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
30723079
if (INTEL_GEN(dev_priv) >= 12) {
3073-
modifiers = gen12_get_plane_modifiers(plane_id);
3080+
modifiers = gen12_get_plane_modifiers(dev_priv, plane_id);
30743081
plane_funcs = &gen12_plane_funcs;
30753082
} else {
30763083
if (plane->has_ccs)

‎drivers/gpu/drm/i915/gt/intel_rps.c

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -81,13 +81,14 @@ static void rps_enable_interrupts(struct intel_rps *rps)
8181
events = (GEN6_PM_RP_UP_THRESHOLD |
8282
GEN6_PM_RP_DOWN_THRESHOLD |
8383
GEN6_PM_RP_DOWN_TIMEOUT);
84-
8584
WRITE_ONCE(rps->pm_events, events);
85+
8686
spin_lock_irq(&gt->irq_lock);
8787
gen6_gt_pm_enable_irq(gt, rps->pm_events);
8888
spin_unlock_irq(&gt->irq_lock);
8989

90-
set(gt->uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, rps->cur_freq));
90+
intel_uncore_write(gt->uncore,
91+
GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq));
9192
}
9293

9394
static void gen6_rps_reset_interrupts(struct intel_rps *rps)
@@ -120,7 +121,9 @@ static void rps_disable_interrupts(struct intel_rps *rps)
120121
struct intel_gt *gt = rps_to_gt(rps);
121122

122123
WRITE_ONCE(rps->pm_events, 0);
123-
set(gt->uncore, GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
124+
125+
intel_uncore_write(gt->uncore,
126+
GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
124127

125128
spin_lock_irq(&gt->irq_lock);
126129
gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS);

‎drivers/gpu/drm/i915/i915_drv.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1507,6 +1507,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
15071507
(IS_ICELAKE(p) && IS_REVID(p, since, until))
15081508

15091509
#define TGL_REVID_A0 0x0
1510+
#define TGL_REVID_B0 0x1
1511+
#define TGL_REVID_C0 0x2
15101512

15111513
#define IS_TGL_REVID(p, since, until) \
15121514
(IS_TIGERLAKE(p) && IS_REVID(p, since, until))

‎drivers/gpu/drm/i915/i915_reg.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,8 +34,8 @@
3434
* Follow the style described here for new macros, and while changing existing
3535
* macros. Do **not** mass change existing definitions just to update the style.
3636
*
37-
* Layout
38-
* ~~~~~~
37+
* File Layout
38+
* ~~~~~~~~~~~
3939
*
4040
* Keep helper macros near the top. For example, _PIPE() and friends.
4141
*

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