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bijudasbebarino
bijudas
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bebarino
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clk: versaclock3: Add missing space between ')' and '{'
Add missing space between ')' and '{' for hw.init initialization. While at it, update the macro VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0x0a->0xa. Signed-off-by: Biju Das <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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‎drivers/clk/clk-versaclock3.c

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@
3737
#define VC3_PLL1_M_DIV(n) ((n) & GENMASK(5, 0))
3838

3939
#define VC3_PLL1_VCO_N_DIVIDER 0x9
40-
#define VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0x0a
40+
#define VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0xa
4141

4242
#define VC3_OUT_DIV1_DIV2_CTRL 0xf
4343

@@ -605,7 +605,7 @@ static struct vc3_hw_data clk_pfd_mux[] = {
605605
.offs = VC3_PLL_OP_CTRL,
606606
.bitmsk = BIT(VC3_PLL_OP_CTRL_PLL2_REFIN_SEL)
607607
},
608-
.hw.init = &(struct clk_init_data){
608+
.hw.init = &(struct clk_init_data) {
609609
.name = "pfd2_mux",
610610
.ops = &vc3_pfd_mux_ops,
611611
.parent_data = pfd_mux_parent_data,
@@ -618,7 +618,7 @@ static struct vc3_hw_data clk_pfd_mux[] = {
618618
.offs = VC3_GENERAL_CTR,
619619
.bitmsk = BIT(VC3_GENERAL_CTR_PLL3_REFIN_SEL)
620620
},
621-
.hw.init = &(struct clk_init_data){
621+
.hw.init = &(struct clk_init_data) {
622622
.name = "pfd3_mux",
623623
.ops = &vc3_pfd_mux_ops,
624624
.parent_data = pfd_mux_parent_data,
@@ -636,7 +636,7 @@ static struct vc3_hw_data clk_pfd[] = {
636636
.mdiv1_bitmsk = VC3_PLL1_M_DIV1,
637637
.mdiv2_bitmsk = VC3_PLL1_M_DIV2
638638
},
639-
.hw.init = &(struct clk_init_data){
639+
.hw.init = &(struct clk_init_data) {
640640
.name = "pfd1",
641641
.ops = &vc3_pfd_ops,
642642
.parent_data = &(const struct clk_parent_data) {
@@ -653,7 +653,7 @@ static struct vc3_hw_data clk_pfd[] = {
653653
.mdiv1_bitmsk = VC3_PLL2_M_DIV1,
654654
.mdiv2_bitmsk = VC3_PLL2_M_DIV2
655655
},
656-
.hw.init = &(struct clk_init_data){
656+
.hw.init = &(struct clk_init_data) {
657657
.name = "pfd2",
658658
.ops = &vc3_pfd_ops,
659659
.parent_hws = (const struct clk_hw *[]) {
@@ -670,7 +670,7 @@ static struct vc3_hw_data clk_pfd[] = {
670670
.mdiv1_bitmsk = VC3_PLL3_M_DIV1,
671671
.mdiv2_bitmsk = VC3_PLL3_M_DIV2
672672
},
673-
.hw.init = &(struct clk_init_data){
673+
.hw.init = &(struct clk_init_data) {
674674
.name = "pfd3",
675675
.ops = &vc3_pfd_ops,
676676
.parent_hws = (const struct clk_hw *[]) {
@@ -691,7 +691,7 @@ static struct vc3_hw_data clk_pll[] = {
691691
.vco_min = VC3_PLL1_VCO_MIN,
692692
.vco_max = VC3_PLL1_VCO_MAX
693693
},
694-
.hw.init = &(struct clk_init_data){
694+
.hw.init = &(struct clk_init_data) {
695695
.name = "pll1",
696696
.ops = &vc3_pll_ops,
697697
.parent_hws = (const struct clk_hw *[]) {
@@ -709,7 +709,7 @@ static struct vc3_hw_data clk_pll[] = {
709709
.vco_min = VC3_PLL2_VCO_MIN,
710710
.vco_max = VC3_PLL2_VCO_MAX
711711
},
712-
.hw.init = &(struct clk_init_data){
712+
.hw.init = &(struct clk_init_data) {
713713
.name = "pll2",
714714
.ops = &vc3_pll_ops,
715715
.parent_hws = (const struct clk_hw *[]) {
@@ -727,7 +727,7 @@ static struct vc3_hw_data clk_pll[] = {
727727
.vco_min = VC3_PLL3_VCO_MIN,
728728
.vco_max = VC3_PLL3_VCO_MAX
729729
},
730-
.hw.init = &(struct clk_init_data){
730+
.hw.init = &(struct clk_init_data) {
731731
.name = "pll3",
732732
.ops = &vc3_pll_ops,
733733
.parent_hws = (const struct clk_hw *[]) {
@@ -760,7 +760,7 @@ static struct vc3_hw_data clk_div_mux[] = {
760760
.offs = VC3_GENERAL_CTR,
761761
.bitmsk = VC3_GENERAL_CTR_DIV1_SRC_SEL
762762
},
763-
.hw.init = &(struct clk_init_data){
763+
.hw.init = &(struct clk_init_data) {
764764
.name = "div1_mux",
765765
.ops = &vc3_div_mux_ops,
766766
.parent_data = div_mux_parent_data[VC3_DIV1_MUX],
@@ -773,7 +773,7 @@ static struct vc3_hw_data clk_div_mux[] = {
773773
.offs = VC3_PLL3_CHARGE_PUMP_CTRL,
774774
.bitmsk = VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL
775775
},
776-
.hw.init = &(struct clk_init_data){
776+
.hw.init = &(struct clk_init_data) {
777777
.name = "div3_mux",
778778
.ops = &vc3_div_mux_ops,
779779
.parent_data = div_mux_parent_data[VC3_DIV3_MUX],
@@ -786,7 +786,7 @@ static struct vc3_hw_data clk_div_mux[] = {
786786
.offs = VC3_OUTPUT_CTR,
787787
.bitmsk = VC3_OUTPUT_CTR_DIV4_SRC_SEL
788788
},
789-
.hw.init = &(struct clk_init_data){
789+
.hw.init = &(struct clk_init_data) {
790790
.name = "div4_mux",
791791
.ops = &vc3_div_mux_ops,
792792
.parent_data = div_mux_parent_data[VC3_DIV4_MUX],
@@ -805,7 +805,7 @@ static struct vc3_hw_data clk_div[] = {
805805
.width = 4,
806806
.flags = CLK_DIVIDER_READ_ONLY
807807
},
808-
.hw.init = &(struct clk_init_data){
808+
.hw.init = &(struct clk_init_data) {
809809
.name = "div1",
810810
.ops = &vc3_div_ops,
811811
.parent_hws = (const struct clk_hw *[]) {
@@ -823,7 +823,7 @@ static struct vc3_hw_data clk_div[] = {
823823
.width = 4,
824824
.flags = CLK_DIVIDER_READ_ONLY
825825
},
826-
.hw.init = &(struct clk_init_data){
826+
.hw.init = &(struct clk_init_data) {
827827
.name = "div2",
828828
.ops = &vc3_div_ops,
829829
.parent_hws = (const struct clk_hw *[]) {
@@ -841,7 +841,7 @@ static struct vc3_hw_data clk_div[] = {
841841
.width = 4,
842842
.flags = CLK_DIVIDER_READ_ONLY
843843
},
844-
.hw.init = &(struct clk_init_data){
844+
.hw.init = &(struct clk_init_data) {
845845
.name = "div3",
846846
.ops = &vc3_div_ops,
847847
.parent_hws = (const struct clk_hw *[]) {
@@ -859,7 +859,7 @@ static struct vc3_hw_data clk_div[] = {
859859
.width = 4,
860860
.flags = CLK_DIVIDER_READ_ONLY
861861
},
862-
.hw.init = &(struct clk_init_data){
862+
.hw.init = &(struct clk_init_data) {
863863
.name = "div4",
864864
.ops = &vc3_div_ops,
865865
.parent_hws = (const struct clk_hw *[]) {
@@ -877,7 +877,7 @@ static struct vc3_hw_data clk_div[] = {
877877
.width = 4,
878878
.flags = CLK_DIVIDER_READ_ONLY
879879
},
880-
.hw.init = &(struct clk_init_data){
880+
.hw.init = &(struct clk_init_data) {
881881
.name = "div5",
882882
.ops = &vc3_div_ops,
883883
.parent_hws = (const struct clk_hw *[]) {
@@ -895,7 +895,7 @@ static struct vc3_hw_data clk_mux[] = {
895895
.offs = VC3_SE1_DIV4_CTRL,
896896
.bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL
897897
},
898-
.hw.init = &(struct clk_init_data){
898+
.hw.init = &(struct clk_init_data) {
899899
.name = "se1_mux",
900900
.ops = &vc3_clk_mux_ops,
901901
.parent_hws = (const struct clk_hw *[]) {
@@ -911,7 +911,7 @@ static struct vc3_hw_data clk_mux[] = {
911911
.offs = VC3_SE2_CTRL_REG0,
912912
.bitmsk = VC3_SE2_CTRL_REG0_SE2_CLK_SEL
913913
},
914-
.hw.init = &(struct clk_init_data){
914+
.hw.init = &(struct clk_init_data) {
915915
.name = "se2_mux",
916916
.ops = &vc3_clk_mux_ops,
917917
.parent_hws = (const struct clk_hw *[]) {
@@ -927,7 +927,7 @@ static struct vc3_hw_data clk_mux[] = {
927927
.offs = VC3_SE3_DIFF1_CTRL_REG,
928928
.bitmsk = VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL
929929
},
930-
.hw.init = &(struct clk_init_data){
930+
.hw.init = &(struct clk_init_data) {
931931
.name = "se3_mux",
932932
.ops = &vc3_clk_mux_ops,
933933
.parent_hws = (const struct clk_hw *[]) {
@@ -943,7 +943,7 @@ static struct vc3_hw_data clk_mux[] = {
943943
.offs = VC3_DIFF1_CTRL_REG,
944944
.bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL
945945
},
946-
.hw.init = &(struct clk_init_data){
946+
.hw.init = &(struct clk_init_data) {
947947
.name = "diff1_mux",
948948
.ops = &vc3_clk_mux_ops,
949949
.parent_hws = (const struct clk_hw *[]) {
@@ -959,7 +959,7 @@ static struct vc3_hw_data clk_mux[] = {
959959
.offs = VC3_DIFF2_CTRL_REG,
960960
.bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL
961961
},
962-
.hw.init = &(struct clk_init_data){
962+
.hw.init = &(struct clk_init_data) {
963963
.name = "diff2_mux",
964964
.ops = &vc3_clk_mux_ops,
965965
.parent_hws = (const struct clk_hw *[]) {

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