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278 | 278 | pinctrl-0 = <&pcie_pins>;
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279 | 279 | pinctrl-names = "default";
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280 | 280 |
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281 |
| - pci@0,0 { |
| 281 | + port00: pci@0,0 { |
282 | 282 | device_type = "pci";
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283 | 283 | reg = <0x0 0x0 0x0 0x0 0x0>;
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284 | 284 | reset-gpios = <&pinctrl_ap 152 0>;
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287 | 287 | #address-cells = <3>;
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288 | 288 | #size-cells = <2>;
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289 | 289 | ranges;
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| 290 | + |
| 291 | + interrupt-controller; |
| 292 | + #interrupt-cells = <1>; |
| 293 | + |
| 294 | + interrupt-map-mask = <0 0 0 7>; |
| 295 | + interrupt-map = <0 0 0 1 &port00 0 0 0 0>, |
| 296 | + <0 0 0 2 &port00 0 0 0 1>, |
| 297 | + <0 0 0 3 &port00 0 0 0 2>, |
| 298 | + <0 0 0 4 &port00 0 0 0 3>; |
290 | 299 | };
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291 | 300 |
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292 |
| - pci@1,0 { |
| 301 | + port01: pci@1,0 { |
293 | 302 | device_type = "pci";
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294 | 303 | reg = <0x800 0x0 0x0 0x0 0x0>;
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295 | 304 | reset-gpios = <&pinctrl_ap 153 0>;
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298 | 307 | #address-cells = <3>;
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299 | 308 | #size-cells = <2>;
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300 | 309 | ranges;
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| 310 | + |
| 311 | + interrupt-controller; |
| 312 | + #interrupt-cells = <1>; |
| 313 | + |
| 314 | + interrupt-map-mask = <0 0 0 7>; |
| 315 | + interrupt-map = <0 0 0 1 &port01 0 0 0 0>, |
| 316 | + <0 0 0 2 &port01 0 0 0 1>, |
| 317 | + <0 0 0 3 &port01 0 0 0 2>, |
| 318 | + <0 0 0 4 &port01 0 0 0 3>; |
301 | 319 | };
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302 | 320 |
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303 |
| - pci@2,0 { |
| 321 | + port02: pci@2,0 { |
304 | 322 | device_type = "pci";
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305 | 323 | reg = <0x1000 0x0 0x0 0x0 0x0>;
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306 | 324 | reset-gpios = <&pinctrl_ap 33 0>;
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309 | 327 | #address-cells = <3>;
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310 | 328 | #size-cells = <2>;
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311 | 329 | ranges;
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| 330 | + |
| 331 | + interrupt-controller; |
| 332 | + #interrupt-cells = <1>; |
| 333 | + |
| 334 | + interrupt-map-mask = <0 0 0 7>; |
| 335 | + interrupt-map = <0 0 0 1 &port02 0 0 0 0>, |
| 336 | + <0 0 0 2 &port02 0 0 0 1>, |
| 337 | + <0 0 0 3 &port02 0 0 0 2>, |
| 338 | + <0 0 0 4 &port02 0 0 0 3>; |
312 | 339 | };
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313 | 340 | };
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314 | 341 | };
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