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| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/timer/realtek,otto-timer.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Realtek Otto SoCs Timer/Counter |
| 8 | + |
| 9 | +description: |
| 10 | + Realtek SoCs support a number of timers/counters. These are used |
| 11 | + as a per CPU clock event generator and an overall CPU clocksource. |
| 12 | + |
| 13 | +maintainers: |
| 14 | + - Chris Packham <[email protected]> |
| 15 | + |
| 16 | +properties: |
| 17 | + $nodename: |
| 18 | + pattern: "^timer@[0-9a-f]+$" |
| 19 | + |
| 20 | + compatible: |
| 21 | + items: |
| 22 | + - enum: |
| 23 | + - realtek,rtl9302-timer |
| 24 | + - const: realtek,otto-timer |
| 25 | + |
| 26 | + reg: |
| 27 | + items: |
| 28 | + - description: timer0 registers |
| 29 | + - description: timer1 registers |
| 30 | + - description: timer2 registers |
| 31 | + - description: timer3 registers |
| 32 | + - description: timer4 registers |
| 33 | + |
| 34 | + clocks: |
| 35 | + maxItems: 1 |
| 36 | + |
| 37 | + interrupts: |
| 38 | + items: |
| 39 | + - description: timer0 interrupt |
| 40 | + - description: timer1 interrupt |
| 41 | + - description: timer2 interrupt |
| 42 | + - description: timer3 interrupt |
| 43 | + - description: timer4 interrupt |
| 44 | + |
| 45 | +required: |
| 46 | + - compatible |
| 47 | + - reg |
| 48 | + - clocks |
| 49 | + - interrupts |
| 50 | + |
| 51 | +additionalProperties: false |
| 52 | + |
| 53 | +examples: |
| 54 | + - | |
| 55 | + timer@3200 { |
| 56 | + compatible = "realtek,rtl9302-timer", "realtek,otto-timer"; |
| 57 | + reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>, |
| 58 | + <0x3230 0x10>, <0x3240 0x10>; |
| 59 | +
|
| 60 | + interrupt-parent = <&intc>; |
| 61 | + interrupts = <7>, <8>, <9>, <10>, <11>; |
| 62 | + clocks = <&lx_clk>; |
| 63 | + }; |
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