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bpankajlzhenyw
bpankajl
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zhenyw
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drm/i915/gvt: Make WARN* drm specific where vgpu ptr is available
Drm specific drm_WARN* calls include device information in the backtrace, so we know what device the warnings originate from. Covert all the calls of WARN* with device specific drm_WARN* variants in functions where drm_device struct pointer is readily available. The conversion was done automatically with below coccinelle semantic patch. checkpatch errors/warnings are fixed manually. @@ identifier func, T; @@ func(struct intel_vgpu *T,...) { +struct drm_i915_private *i915 = T->gvt->dev_priv; <+... ( -WARN( +drm_WARN(&i915->drm, ...) | -WARN_ON( +drm_WARN_ON(&i915->drm, ...) | -WARN_ONCE( +drm_WARN_ONCE(&i915->drm, ...) | -WARN_ON_ONCE( +drm_WARN_ON_ONCE(&i915->drm, ...) ) ...+> } Signed-off-by: Pankaj Bharadiya <[email protected]> Acked-by: Zhenyu Wang <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
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11 files changed

+104
-53
lines changed

11 files changed

+104
-53
lines changed

‎drivers/gpu/drm/i915/gvt/cfg_space.c

Lines changed: 14 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -106,10 +106,13 @@ static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off,
106106
int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
107107
void *p_data, unsigned int bytes)
108108
{
109-
if (WARN_ON(bytes > 4))
109+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
110+
111+
if (drm_WARN_ON(&i915->drm, bytes > 4))
110112
return -EINVAL;
111113

112-
if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))
114+
if (drm_WARN_ON(&i915->drm,
115+
offset + bytes > vgpu->gvt->device_info.cfg_space_size))
113116
return -EINVAL;
114117

115118
memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes);
@@ -297,42 +300,44 @@ static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,
297300
int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
298301
void *p_data, unsigned int bytes)
299302
{
303+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
300304
int ret;
301305

302-
if (WARN_ON(bytes > 4))
306+
if (drm_WARN_ON(&i915->drm, bytes > 4))
303307
return -EINVAL;
304308

305-
if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))
309+
if (drm_WARN_ON(&i915->drm,
310+
offset + bytes > vgpu->gvt->device_info.cfg_space_size))
306311
return -EINVAL;
307312

308313
/* First check if it's PCI_COMMAND */
309314
if (IS_ALIGNED(offset, 2) && offset == PCI_COMMAND) {
310-
if (WARN_ON(bytes > 2))
315+
if (drm_WARN_ON(&i915->drm, bytes > 2))
311316
return -EINVAL;
312317
return emulate_pci_command_write(vgpu, offset, p_data, bytes);
313318
}
314319

315320
switch (rounddown(offset, 4)) {
316321
case PCI_ROM_ADDRESS:
317-
if (WARN_ON(!IS_ALIGNED(offset, 4)))
322+
if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
318323
return -EINVAL;
319324
return emulate_pci_rom_bar_write(vgpu, offset, p_data, bytes);
320325

321326
case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5:
322-
if (WARN_ON(!IS_ALIGNED(offset, 4)))
327+
if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
323328
return -EINVAL;
324329
return emulate_pci_bar_write(vgpu, offset, p_data, bytes);
325330

326331
case INTEL_GVT_PCI_SWSCI:
327-
if (WARN_ON(!IS_ALIGNED(offset, 4)))
332+
if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
328333
return -EINVAL;
329334
ret = intel_vgpu_emulate_opregion_request(vgpu, *(u32 *)p_data);
330335
if (ret)
331336
return ret;
332337
break;
333338

334339
case INTEL_GVT_PCI_OPREGION:
335-
if (WARN_ON(!IS_ALIGNED(offset, 4)))
340+
if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
336341
return -EINVAL;
337342
ret = intel_vgpu_opregion_base_write_handler(vgpu,
338343
*(u32 *)p_data);

‎drivers/gpu/drm/i915/gvt/display.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -320,9 +320,10 @@ static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
320320
static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
321321
int type, unsigned int resolution)
322322
{
323+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
323324
struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
324325

325-
if (WARN_ON(resolution >= GVT_EDID_NUM))
326+
if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM))
326327
return -EINVAL;
327328

328329
port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);

‎drivers/gpu/drm/i915/gvt/edid.c

Lines changed: 12 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -276,7 +276,9 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
276276
static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
277277
void *p_data, unsigned int bytes)
278278
{
279-
WARN_ON(1);
279+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
280+
281+
drm_WARN_ON(&i915->drm, 1);
280282
return 0;
281283
}
282284

@@ -371,7 +373,9 @@ static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
371373
int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
372374
unsigned int offset, void *p_data, unsigned int bytes)
373375
{
374-
if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
376+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
377+
378+
if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
375379
return -EINVAL;
376380

377381
if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
@@ -399,7 +403,9 @@ int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
399403
int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
400404
unsigned int offset, void *p_data, unsigned int bytes)
401405
{
402-
if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
406+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
407+
408+
if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
403409
return -EINVAL;
404410

405411
if (offset == i915_mmio_reg_offset(PCH_GMBUS0))
@@ -473,6 +479,7 @@ void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
473479
unsigned int offset,
474480
void *p_data)
475481
{
482+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
476483
struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
477484
int msg_length, ret_msg_size;
478485
int msg, addr, ctrl, op;
@@ -532,9 +539,9 @@ void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
532539
* support the gfx driver to do EDID access.
533540
*/
534541
} else {
535-
if (WARN_ON((op & 0x1) != GVT_AUX_I2C_READ))
542+
if (drm_WARN_ON(&i915->drm, (op & 0x1) != GVT_AUX_I2C_READ))
536543
return;
537-
if (WARN_ON(msg_length != 4))
544+
if (drm_WARN_ON(&i915->drm, msg_length != 4))
538545
return;
539546
if (i2c_edid->edid_available && i2c_edid->slave_selected) {
540547
unsigned char val = edid_get_byte(vgpu);

‎drivers/gpu/drm/i915/gvt/gtt.c

Lines changed: 15 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -71,8 +71,10 @@ bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
7171
/* translate a guest gmadr to host gmadr */
7272
int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
7373
{
74-
if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr),
75-
"invalid guest gmadr %llx\n", g_addr))
74+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
75+
76+
if (drm_WARN(&i915->drm, !vgpu_gmadr_is_valid(vgpu, g_addr),
77+
"invalid guest gmadr %llx\n", g_addr))
7678
return -EACCES;
7779

7880
if (vgpu_gmadr_is_aperture(vgpu, g_addr))
@@ -87,8 +89,10 @@ int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)
8789
/* translate a host gmadr to guest gmadr */
8890
int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)
8991
{
90-
if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr),
91-
"invalid host gmadr %llx\n", h_addr))
92+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
93+
94+
if (drm_WARN(&i915->drm, !gvt_gmadr_is_valid(vgpu->gvt, h_addr),
95+
"invalid host gmadr %llx\n", h_addr))
9296
return -EACCES;
9397

9498
if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
@@ -940,6 +944,7 @@ static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt);
940944
static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
941945
struct intel_gvt_gtt_entry *e)
942946
{
947+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
943948
struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
944949
struct intel_vgpu_ppgtt_spt *s;
945950
enum intel_gvt_gtt_type cur_pt_type;
@@ -952,7 +957,9 @@ static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
952957

953958
if (!gtt_type_is_pt(cur_pt_type) ||
954959
!gtt_type_is_pt(cur_pt_type + 1)) {
955-
WARN(1, "Invalid page table type, cur_pt_type is: %d\n", cur_pt_type);
960+
drm_WARN(&i915->drm, 1,
961+
"Invalid page table type, cur_pt_type is: %d\n",
962+
cur_pt_type);
956963
return -EINVAL;
957964
}
958965

@@ -2343,6 +2350,7 @@ int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
23432350
static int alloc_scratch_pages(struct intel_vgpu *vgpu,
23442351
enum intel_gvt_gtt_type type)
23452352
{
2353+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
23462354
struct intel_vgpu_gtt *gtt = &vgpu->gtt;
23472355
struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
23482356
int page_entry_num = I915_GTT_PAGE_SIZE >>
@@ -2352,7 +2360,8 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu,
23522360
struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;
23532361
dma_addr_t daddr;
23542362

2355-
if (WARN_ON(type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX))
2363+
if (drm_WARN_ON(&i915->drm,
2364+
type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX))
23562365
return -EINVAL;
23572366

23582367
scratch_pt = (void *)get_zeroed_page(GFP_KERNEL);

‎drivers/gpu/drm/i915/gvt/handlers.c

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1306,13 +1306,15 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
13061306
static int pf_write(struct intel_vgpu *vgpu,
13071307
unsigned int offset, void *p_data, unsigned int bytes)
13081308
{
1309+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
13091310
u32 val = *(u32 *)p_data;
13101311

13111312
if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
13121313
offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
13131314
offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
1314-
WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n",
1315-
vgpu->id);
1315+
drm_WARN_ONCE(&i915->drm, true,
1316+
"VM(%d): guest is trying to scaling a plane\n",
1317+
vgpu->id);
13161318
return 0;
13171319
}
13181320

@@ -1360,13 +1362,15 @@ static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
13601362
static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
13611363
void *p_data, unsigned int bytes)
13621364
{
1365+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
13631366
u32 mode;
13641367

13651368
write_vreg(vgpu, offset, p_data, bytes);
13661369
mode = vgpu_vreg(vgpu, offset);
13671370

13681371
if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
1369-
WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n",
1372+
drm_WARN_ONCE(&i915->drm, 1,
1373+
"VM(%d): iGVT-g doesn't support GuC\n",
13701374
vgpu->id);
13711375
return 0;
13721376
}
@@ -1377,10 +1381,12 @@ static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
13771381
static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
13781382
void *p_data, unsigned int bytes)
13791383
{
1384+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
13801385
u32 trtte = *(u32 *)p_data;
13811386

13821387
if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
1383-
WARN(1, "VM(%d): Use physical address for TRTT!\n",
1388+
drm_WARN(&i915->drm, 1,
1389+
"VM(%d): Use physical address for TRTT!\n",
13841390
vgpu->id);
13851391
return -EINVAL;
13861392
}
@@ -1682,12 +1688,13 @@ static int mmio_read_from_hw(struct intel_vgpu *vgpu,
16821688
static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
16831689
void *p_data, unsigned int bytes)
16841690
{
1691+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
16851692
int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
16861693
struct intel_vgpu_execlist *execlist;
16871694
u32 data = *(u32 *)p_data;
16881695
int ret = 0;
16891696

1690-
if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES))
1697+
if (drm_WARN_ON(&i915->drm, ring_id < 0 || ring_id >= I915_NUM_ENGINES))
16911698
return -EINVAL;
16921699

16931700
execlist = &vgpu->submission.execlist[ring_id];
@@ -3541,13 +3548,14 @@ bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
35413548
int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
35423549
void *pdata, unsigned int bytes, bool is_read)
35433550
{
3551+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
35443552
struct intel_gvt *gvt = vgpu->gvt;
35453553
struct intel_gvt_mmio_info *mmio_info;
35463554
struct gvt_mmio_block *mmio_block;
35473555
gvt_mmio_func func;
35483556
int ret;
35493557

3550-
if (WARN_ON(bytes > 8))
3558+
if (drm_WARN_ON(&i915->drm, bytes > 8))
35513559
return -EINVAL;
35523560

35533561
/*

‎drivers/gpu/drm/i915/gvt/interrupt.c

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -244,6 +244,7 @@ int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
244244
int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
245245
unsigned int reg, void *p_data, unsigned int bytes)
246246
{
247+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
247248
struct intel_gvt *gvt = vgpu->gvt;
248249
struct intel_gvt_irq_ops *ops = gvt->irq.ops;
249250
struct intel_gvt_irq_info *info;
@@ -255,7 +256,7 @@ int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
255256
vgpu_vreg(vgpu, reg) = ier;
256257

257258
info = regbase_to_irq_info(gvt, ier_to_regbase(reg));
258-
if (WARN_ON(!info))
259+
if (drm_WARN_ON(&i915->drm, !info))
259260
return -EINVAL;
260261

261262
if (info->has_upstream_irq)
@@ -282,14 +283,15 @@ int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
282283
int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
283284
void *p_data, unsigned int bytes)
284285
{
286+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
285287
struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt,
286288
iir_to_regbase(reg));
287289
u32 iir = *(u32 *)p_data;
288290

289291
trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
290292
(vgpu_vreg(vgpu, reg) ^ iir));
291293

292-
if (WARN_ON(!info))
294+
if (drm_WARN_ON(&i915->drm, !info))
293295
return -EINVAL;
294296

295297
vgpu_vreg(vgpu, reg) &= ~iir;
@@ -319,6 +321,7 @@ static struct intel_gvt_irq_map gen8_irq_map[] = {
319321
static void update_upstream_irq(struct intel_vgpu *vgpu,
320322
struct intel_gvt_irq_info *info)
321323
{
324+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
322325
struct intel_gvt_irq *irq = &vgpu->gvt->irq;
323326
struct intel_gvt_irq_map *map = irq->irq_map;
324327
struct intel_gvt_irq_info *up_irq_info = NULL;
@@ -340,7 +343,8 @@ static void update_upstream_irq(struct intel_vgpu *vgpu,
340343
if (!up_irq_info)
341344
up_irq_info = irq->info[map->up_irq_group];
342345
else
343-
WARN_ON(up_irq_info != irq->info[map->up_irq_group]);
346+
drm_WARN_ON(&i915->drm, up_irq_info !=
347+
irq->info[map->up_irq_group]);
344348

345349
bit = map->up_irq_bit;
346350

@@ -350,7 +354,7 @@ static void update_upstream_irq(struct intel_vgpu *vgpu,
350354
clear_bits |= (1 << bit);
351355
}
352356

353-
if (WARN_ON(!up_irq_info))
357+
if (drm_WARN_ON(&i915->drm, !up_irq_info))
354358
return;
355359

356360
if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) {
@@ -618,13 +622,14 @@ static struct intel_gvt_irq_ops gen8_irq_ops = {
618622
void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
619623
enum intel_gvt_event_type event)
620624
{
625+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
621626
struct intel_gvt *gvt = vgpu->gvt;
622627
struct intel_gvt_irq *irq = &gvt->irq;
623628
gvt_event_virt_handler_t handler;
624629
struct intel_gvt_irq_ops *ops = gvt->irq.ops;
625630

626631
handler = get_event_virt_handler(irq, event);
627-
WARN_ON(!handler);
632+
drm_WARN_ON(&i915->drm, !handler);
628633

629634
handler(irq, event, vgpu);
630635

‎drivers/gpu/drm/i915/gvt/kvmgt.c

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -150,6 +150,7 @@ static bool kvmgt_guest_exit(struct kvmgt_guest_info *info);
150150
static void gvt_unpin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn,
151151
unsigned long size)
152152
{
153+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
153154
int total_pages;
154155
int npage;
155156
int ret;
@@ -160,7 +161,7 @@ static void gvt_unpin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn,
160161
unsigned long cur_gfn = gfn + npage;
161162

162163
ret = vfio_unpin_pages(mdev_dev(kvmgt_vdev(vgpu)->mdev), &cur_gfn, 1);
163-
WARN_ON(ret != 1);
164+
drm_WARN_ON(&i915->drm, ret != 1);
164165
}
165166
}
166167

@@ -854,6 +855,7 @@ static void intel_vgpu_release_msi_eventfd_ctx(struct intel_vgpu *vgpu)
854855
static void __intel_vgpu_release(struct intel_vgpu *vgpu)
855856
{
856857
struct kvmgt_vdev *vdev = kvmgt_vdev(vgpu);
858+
struct drm_i915_private *i915 = vgpu->gvt->dev_priv;
857859
struct kvmgt_guest_info *info;
858860
int ret;
859861

@@ -867,11 +869,13 @@ static void __intel_vgpu_release(struct intel_vgpu *vgpu)
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ret = vfio_unregister_notifier(mdev_dev(vdev->mdev), VFIO_IOMMU_NOTIFY,
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&vdev->iommu_notifier);
870-
WARN(ret, "vfio_unregister_notifier for iommu failed: %d\n", ret);
872+
drm_WARN(&i915->drm, ret,
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"vfio_unregister_notifier for iommu failed: %d\n", ret);
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ret = vfio_unregister_notifier(mdev_dev(vdev->mdev), VFIO_GROUP_NOTIFY,
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&vdev->group_notifier);
874-
WARN(ret, "vfio_unregister_notifier for group failed: %d\n", ret);
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drm_WARN(&i915->drm, ret,
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"vfio_unregister_notifier for group failed: %d\n", ret);
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/* dereference module reference taken at open */
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module_put(THIS_MODULE);

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