Skip to content

Commit 13a7733

Browse files
bjorn-helgaasbjorn-helgaas
committed
Merge branch 'remotes/lorenzo/pci/cadence'
- Convert cadence to use standard "dma-ranges" DT property instead of its own "cdns,no-bar-match-nbits" (Kishon Vijay Abraham I) - Fix pm_runtime_put_sync() issues in cadence error paths (Kishon Vijay Abraham I) - Add PTR_ALIGN_DOWN macro (Kishon Vijay Abraham I) - Convert cadence r/w accessors to only 32-bit accesses (Kishon Vijay Abraham I) - Add cadence support to start Link and check Link status (Kishon Vijay Abraham I) - Allow custom PCI ops for cadence-based drivers (Kishon Vijay Abraham I) - Remove "mem" from cadence reg binding since it's not memory and it overlaps the PCIe config and memory region (Kishon Vijay Abraham I) - Add cadence ->cpu_addr_fixup() for platforms that require absolute addresses in the ATU, not just offsets (Kishon Vijay Abraham I) - Update cadence Vendor IDs using local management registers, not architected config space (Kishon Vijay Abraham I) - Add cadence endpoint driver MSI-X support (Kishon Vijay Abraham I) - Add bindings and driver for TI J721E SoC, supporting both host and endpoint mode (Kishon Vijay Abraham I) * remotes/lorenzo/pci/cadence: MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe misc: pci_endpoint_test: Add J721E in pci_device_id table PCI: j721e: Add TI J721E PCIe driver dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC PCI: cadence: Add MSI-X support to Endpoint driver PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register PCI: cadence: Add new *ops* for CPU addr fixup dt-bindings: PCI: cadence: Remove "mem" from reg binding PCI: cadence: Allow pci_host_bridge to have custom pci_ops PCI: cadence: Add support to start link and verify link status PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses linux/kernel.h: Add PTR_ALIGN_DOWN macro PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path PCI: cadence: Use "dma-ranges" instead of "cdns,no-bar-match-nbits" property
2 parents 5b17dba + 0dbe77c commit 13a7733

File tree

14 files changed

+1297
-70
lines changed

14 files changed

+1297
-70
lines changed

‎Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -18,13 +18,12 @@ properties:
1818
const: cdns,cdns-pcie-host
1919

2020
reg:
21-
maxItems: 3
21+
maxItems: 2
2222

2323
reg-names:
2424
items:
2525
- const: reg
2626
- const: cfg
27-
- const: mem
2827

2928
msi-parent: true
3029

@@ -49,9 +48,8 @@ examples:
4948
device-id = <0x0200>;
5049
5150
reg = <0x0 0xfb000000 0x0 0x01000000>,
52-
<0x0 0x41000000 0x0 0x00001000>,
53-
<0x0 0x40000000 0x0 0x04000000>;
54-
reg-names = "reg", "cfg", "mem";
51+
<0x0 0x41000000 0x0 0x00001000>;
52+
reg-names = "reg", "cfg";
5553
5654
ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
5755
<0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;

‎Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml

Lines changed: 94 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,94 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3+
%YAML 1.2
4+
---
5+
$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
6+
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7+
8+
title: TI J721E PCI EP (PCIe Wrapper)
9+
10+
maintainers:
11+
- Kishon Vijay Abraham I <[email protected]>
12+
13+
allOf:
14+
- $ref: "cdns-pcie-ep.yaml#"
15+
16+
properties:
17+
compatible:
18+
enum:
19+
- ti,j721e-pcie-ep
20+
21+
reg:
22+
maxItems: 4
23+
24+
reg-names:
25+
items:
26+
- const: intd_cfg
27+
- const: user_cfg
28+
- const: reg
29+
- const: mem
30+
31+
ti,syscon-pcie-ctrl:
32+
description: Phandle to the SYSCON entry required for configuring PCIe mode
33+
and link speed.
34+
allOf:
35+
- $ref: /schemas/types.yaml#/definitions/phandle
36+
37+
power-domains:
38+
maxItems: 1
39+
40+
clocks:
41+
maxItems: 1
42+
description: clock-specifier to represent input to the PCIe
43+
44+
clock-names:
45+
items:
46+
- const: fck
47+
48+
dma-coherent:
49+
description: Indicates that the PCIe IP block can ensure the coherency
50+
51+
required:
52+
- compatible
53+
- reg
54+
- reg-names
55+
- ti,syscon-pcie-ctrl
56+
- max-link-speed
57+
- num-lanes
58+
- power-domains
59+
- clocks
60+
- clock-names
61+
- cdns,max-outbound-regions
62+
- dma-coherent
63+
- max-functions
64+
- phys
65+
- phy-names
66+
67+
examples:
68+
- |
69+
#include <dt-bindings/soc/ti,sci_pm_domain.h>
70+
71+
bus {
72+
#address-cells = <2>;
73+
#size-cells = <2>;
74+
75+
pcie0_ep: pcie-ep@d000000 {
76+
compatible = "ti,j721e-pcie-ep";
77+
reg = <0x00 0x02900000 0x00 0x1000>,
78+
<0x00 0x02907000 0x00 0x400>,
79+
<0x00 0x0d000000 0x00 0x00800000>,
80+
<0x00 0x10000000 0x00 0x08000000>;
81+
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
82+
ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
83+
max-link-speed = <3>;
84+
num-lanes = <2>;
85+
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
86+
clocks = <&k3_clks 239 1>;
87+
clock-names = "fck";
88+
cdns,max-outbound-regions = <16>;
89+
max-functions = /bits/ 8 <6>;
90+
dma-coherent;
91+
phys = <&serdes0_pcie_link>;
92+
phy-names = "pcie-phy";
93+
};
94+
};

‎Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml

Lines changed: 113 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,113 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
3+
%YAML 1.2
4+
---
5+
$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"
6+
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7+
8+
title: TI J721E PCI Host (PCIe Wrapper)
9+
10+
maintainers:
11+
- Kishon Vijay Abraham I <[email protected]>
12+
13+
allOf:
14+
- $ref: "cdns-pcie-host.yaml#"
15+
16+
properties:
17+
compatible:
18+
enum:
19+
- ti,j721e-pcie-host
20+
21+
reg:
22+
maxItems: 4
23+
24+
reg-names:
25+
items:
26+
- const: intd_cfg
27+
- const: user_cfg
28+
- const: reg
29+
- const: cfg
30+
31+
ti,syscon-pcie-ctrl:
32+
description: Phandle to the SYSCON entry required for configuring PCIe mode
33+
and link speed.
34+
allOf:
35+
- $ref: /schemas/types.yaml#/definitions/phandle
36+
37+
power-domains:
38+
maxItems: 1
39+
40+
clocks:
41+
maxItems: 1
42+
description: clock-specifier to represent input to the PCIe
43+
44+
clock-names:
45+
items:
46+
- const: fck
47+
48+
vendor-id:
49+
const: 0x104c
50+
51+
device-id:
52+
const: 0xb00d
53+
54+
msi-map: true
55+
56+
required:
57+
- compatible
58+
- reg
59+
- reg-names
60+
- ti,syscon-pcie-ctrl
61+
- max-link-speed
62+
- num-lanes
63+
- power-domains
64+
- clocks
65+
- clock-names
66+
- vendor-id
67+
- device-id
68+
- msi-map
69+
- dma-coherent
70+
- dma-ranges
71+
- ranges
72+
- reset-gpios
73+
- phys
74+
- phy-names
75+
76+
examples:
77+
- |
78+
#include <dt-bindings/soc/ti,sci_pm_domain.h>
79+
#include <dt-bindings/gpio/gpio.h>
80+
81+
bus {
82+
#address-cells = <2>;
83+
#size-cells = <2>;
84+
85+
pcie0_rc: pcie@2900000 {
86+
compatible = "ti,j721e-pcie-host";
87+
reg = <0x00 0x02900000 0x00 0x1000>,
88+
<0x00 0x02907000 0x00 0x400>,
89+
<0x00 0x0d000000 0x00 0x00800000>,
90+
<0x00 0x10000000 0x00 0x00001000>;
91+
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
92+
ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
93+
max-link-speed = <3>;
94+
num-lanes = <2>;
95+
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
96+
clocks = <&k3_clks 239 1>;
97+
clock-names = "fck";
98+
device_type = "pci";
99+
#address-cells = <3>;
100+
#size-cells = <2>;
101+
bus-range = <0x0 0xf>;
102+
vendor-id = <0x104c>;
103+
device-id = <0xb00d>;
104+
msi-map = <0x0 &gic_its 0x0 0x10000>;
105+
dma-coherent;
106+
reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
107+
phys = <&serdes0_pcie_link>;
108+
phy-names = "pcie-phy";
109+
ranges = <0x01000000 0x0 0x10001000 0x00 0x10001000 0x0 0x0010000>,
110+
<0x02000000 0x0 0x10011000 0x00 0x10011000 0x0 0x7fef000>;
111+
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
112+
};
113+
};

‎MAINTAINERS

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13149,12 +13149,14 @@ S: Maintained
1314913149
F: Documentation/devicetree/bindings/pci/designware-pcie.txt
1315013150
F: drivers/pci/controller/dwc/*designware*
1315113151

13152-
PCI DRIVER FOR TI DRA7XX
13152+
PCI DRIVER FOR TI DRA7XX/J721E
1315313153
M: Kishon Vijay Abraham I <[email protected]>
1315413154
L: [email protected]
1315513155
L: [email protected]
13156+
L: [email protected]
1315613157
S: Supported
1315713158
F: Documentation/devicetree/bindings/pci/ti-pci.txt
13159+
F: drivers/pci/controller/cadence/pci-j721e.c
1315813160
F: drivers/pci/controller/dwc/pci-dra7xx.c
1315913161

1316013162
PCI DRIVER FOR TI KEYSTONE

‎drivers/misc/pci_endpoint_test.c

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,7 @@
6868
#define PCI_ENDPOINT_TEST_FLAGS 0x2c
6969
#define FLAG_USE_DMA BIT(0)
7070

71+
#define PCI_DEVICE_ID_TI_J721E 0xb00d
7172
#define PCI_DEVICE_ID_TI_AM654 0xb00c
7273

7374
#define is_am654_pci_dev(pdev) \
@@ -932,6 +933,11 @@ static const struct pci_endpoint_test_data am654_data = {
932933
.irq_type = IRQ_TYPE_MSI,
933934
};
934935

936+
static const struct pci_endpoint_test_data j721e_data = {
937+
.alignment = 256,
938+
.irq_type = IRQ_TYPE_MSI,
939+
};
940+
935941
static const struct pci_device_id pci_endpoint_test_tbl[] = {
936942
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x),
937943
.driver_data = (kernel_ulong_t)&default_data,
@@ -946,6 +952,9 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
946952
},
947953
{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),
948954
},
955+
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),
956+
.driver_data = (kernel_ulong_t)&j721e_data,
957+
},
949958
{ }
950959
};
951960
MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);

‎drivers/pci/controller/cadence/Kconfig

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,4 +42,27 @@ config PCIE_CADENCE_PLAT_EP
4242
endpoint mode. This PCIe controller may be embedded into many
4343
different vendors SoCs.
4444

45+
config PCI_J721E
46+
bool
47+
48+
config PCI_J721E_HOST
49+
bool "TI J721E PCIe platform host controller"
50+
depends on OF
51+
select PCIE_CADENCE_HOST
52+
select PCI_J721E
53+
help
54+
Say Y here if you want to support the TI J721E PCIe platform
55+
controller in host mode. TI J721E PCIe controller uses Cadence PCIe
56+
core.
57+
58+
config PCI_J721E_EP
59+
bool "TI J721E PCIe platform endpoint controller"
60+
depends on OF
61+
depends on PCI_ENDPOINT
62+
select PCIE_CADENCE_EP
63+
select PCI_J721E
64+
help
65+
Say Y here if you want to support the TI J721E PCIe platform
66+
controller in endpoint mode. TI J721E PCIe controller uses Cadence PCIe
67+
core.
4568
endmenu

‎drivers/pci/controller/cadence/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,3 +3,4 @@ obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o
33
obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o
44
obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o
55
obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o
6+
obj-$(CONFIG_PCI_J721E) += pci-j721e.o

0 commit comments

Comments
 (0)