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11 | 11 | #include <dt-bindings/interrupt-controller/arm-gic.h>
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12 | 12 | #include <dt-bindings/power/qcom-rpmpd.h>
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13 | 13 | #include <dt-bindings/soc/qcom,rpmh-rsc.h>
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| 14 | +#include <dt-bindings/interconnect/qcom,sdx65.h> |
14 | 15 |
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15 | 16 | / {
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16 | 17 | #address-cells = <1>;
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299 | 300 | #hwlock-cells = <1>;
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300 | 301 | };
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301 | 302 |
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| 303 | + ipa: ipa@3f40000 { |
| 304 | + compatible = "qcom,sdx65-ipa"; |
| 305 | + |
| 306 | + reg = <0x03f40000 0x10000>, |
| 307 | + <0x03f50000 0x5000>, |
| 308 | + <0x03e04000 0xfc000>; |
| 309 | + reg-names = "ipa-reg", |
| 310 | + "ipa-shared", |
| 311 | + "gsi"; |
| 312 | + |
| 313 | + interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, |
| 314 | + <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, |
| 315 | + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
| 316 | + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; |
| 317 | + interrupt-names = "ipa", |
| 318 | + "gsi", |
| 319 | + "ipa-clock-query", |
| 320 | + "ipa-setup-ready"; |
| 321 | + |
| 322 | + iommus = <&apps_smmu 0x5e0 0x0>, |
| 323 | + <&apps_smmu 0x5e2 0x0>; |
| 324 | + |
| 325 | + clocks = <&rpmhcc RPMH_IPA_CLK>; |
| 326 | + clock-names = "core"; |
| 327 | + |
| 328 | + interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI1>, |
| 329 | + <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>; |
| 330 | + interconnect-names = "memory", |
| 331 | + "config"; |
| 332 | + |
| 333 | + qcom,smem-states = <&ipa_smp2p_out 0>, |
| 334 | + <&ipa_smp2p_out 1>; |
| 335 | + qcom,smem-state-names = "ipa-clock-enabled-valid", |
| 336 | + "ipa-clock-enabled"; |
| 337 | + |
| 338 | + status = "disabled"; |
| 339 | + }; |
| 340 | + |
302 | 341 | remoteproc_mpss: remoteproc@4080000 {
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303 | 342 | compatible = "qcom,sdx55-mpss-pas";
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304 | 343 | reg = <0x04080000 0x4040>;
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