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Alex Elderandersson
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ARM: dts: qcom: sdx65: add IPA information
Add IPA-related nodes and definitions to "sdx65.dtsi". The SMP2P nodes (ipa_smp2p_out and ipa_smp2p_in) are already present. Enable IPA in "sdx65-mtp.dts"; this GSI firmware is loaded by Trust Zone on this platform. Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Tested-by: Rohit Agarwal <[email protected]> Signed-off-by: Alex Elder <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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arch/arm/boot/dts/qcom-sdx65-mtp.dts

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@@ -245,6 +245,11 @@
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status = "okay";
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};
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&ipa {
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qcom,gsi-loader = "skip";
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status = "okay";
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};
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&qpic_bam {
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status = "okay";
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};

arch/arm/boot/dts/qcom-sdx65.dtsi

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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/interconnect/qcom,sdx65.h>
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/ {
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#address-cells = <1>;
@@ -299,6 +300,44 @@
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#hwlock-cells = <1>;
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};
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ipa: ipa@3f40000 {
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compatible = "qcom,sdx65-ipa";
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reg = <0x03f40000 0x10000>,
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<0x03f50000 0x5000>,
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<0x03e04000 0xfc000>;
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reg-names = "ipa-reg",
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"ipa-shared",
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"gsi";
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interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
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<&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
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<&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "ipa",
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"gsi",
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"ipa-clock-query",
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"ipa-setup-ready";
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iommus = <&apps_smmu 0x5e0 0x0>,
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<&apps_smmu 0x5e2 0x0>;
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clocks = <&rpmhcc RPMH_IPA_CLK>;
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clock-names = "core";
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interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI1>,
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<&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>;
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interconnect-names = "memory",
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"config";
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qcom,smem-states = <&ipa_smp2p_out 0>,
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<&ipa_smp2p_out 1>;
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qcom,smem-state-names = "ipa-clock-enabled-valid",
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"ipa-clock-enabled";
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status = "disabled";
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};
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remoteproc_mpss: remoteproc@4080000 {
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compatible = "qcom,sdx55-mpss-pas";
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reg = <0x04080000 0x4040>;

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