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airliedairlied
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Merge tag 'amd-drm-fixes-6.11-2024-09-05' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.11-2024-09-05: amdgpu: - IPS workaround - Fix compatibility with older MES firmware - Fix CPU spikes when clearing VRAM - Backlight fix - PMO fix - Revert SWSMU change to fix regression Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents ca10367 + 1a8d845 commit 141bb6b

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8 files changed

+89
-25
lines changed

8 files changed

+89
-25
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -348,6 +348,9 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
348348
return -EINVAL;
349349
}
350350

351+
/* always clear VRAM */
352+
flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
353+
351354
/* create a gem object to contain this object in */
352355
if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
353356
AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -657,7 +657,7 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id)
657657
uint64_t queue_mask = 0;
658658
int r, i, j;
659659

660-
if (adev->enable_mes)
660+
if (adev->mes.enable_legacy_queue_map)
661661
return amdgpu_gfx_mes_enable_kcq(adev, xcc_id);
662662

663663
if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources)
@@ -719,7 +719,7 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id)
719719

720720
amdgpu_device_flush_hdp(adev, NULL);
721721

722-
if (adev->enable_mes) {
722+
if (adev->mes.enable_legacy_queue_map) {
723723
for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
724724
j = i + xcc_id * adev->gfx.num_gfx_rings;
725725
r = amdgpu_mes_map_legacy_queue(adev,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -75,6 +75,7 @@ struct amdgpu_mes {
7575

7676
uint32_t sched_version;
7777
uint32_t kiq_version;
78+
bool enable_legacy_queue_map;
7879

7980
uint32_t total_max_queue;
8081
uint32_t max_doorbell_slices;

‎drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

Lines changed: 34 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -693,6 +693,28 @@ static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev,
693693
(void **)&adev->mes.ucode_fw_ptr[pipe]);
694694
}
695695

696+
static void mes_v11_0_get_fw_version(struct amdgpu_device *adev)
697+
{
698+
int pipe;
699+
700+
/* get MES scheduler/KIQ versions */
701+
mutex_lock(&adev->srbm_mutex);
702+
703+
for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
704+
soc21_grbm_select(adev, 3, pipe, 0, 0);
705+
706+
if (pipe == AMDGPU_MES_SCHED_PIPE)
707+
adev->mes.sched_version =
708+
RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
709+
else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
710+
adev->mes.kiq_version =
711+
RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
712+
}
713+
714+
soc21_grbm_select(adev, 0, 0, 0, 0);
715+
mutex_unlock(&adev->srbm_mutex);
716+
}
717+
696718
static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)
697719
{
698720
uint64_t ucode_addr;
@@ -1062,18 +1084,6 @@ static int mes_v11_0_queue_init(struct amdgpu_device *adev,
10621084
mes_v11_0_queue_init_register(ring);
10631085
}
10641086

1065-
/* get MES scheduler/KIQ versions */
1066-
mutex_lock(&adev->srbm_mutex);
1067-
soc21_grbm_select(adev, 3, pipe, 0, 0);
1068-
1069-
if (pipe == AMDGPU_MES_SCHED_PIPE)
1070-
adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1071-
else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
1072-
adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1073-
1074-
soc21_grbm_select(adev, 0, 0, 0, 0);
1075-
mutex_unlock(&adev->srbm_mutex);
1076-
10771087
return 0;
10781088
}
10791089

@@ -1320,15 +1330,24 @@ static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)
13201330

13211331
mes_v11_0_enable(adev, true);
13221332

1333+
mes_v11_0_get_fw_version(adev);
1334+
13231335
mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring);
13241336

13251337
r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);
13261338
if (r)
13271339
goto failure;
13281340

1329-
r = mes_v11_0_hw_init(adev);
1330-
if (r)
1331-
goto failure;
1341+
if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47)
1342+
adev->mes.enable_legacy_queue_map = true;
1343+
else
1344+
adev->mes.enable_legacy_queue_map = false;
1345+
1346+
if (adev->mes.enable_legacy_queue_map) {
1347+
r = mes_v11_0_hw_init(adev);
1348+
if (r)
1349+
goto failure;
1350+
}
13321351

13331352
return r;
13341353

‎drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1266,6 +1266,7 @@ static int mes_v12_0_sw_init(void *handle)
12661266
adev->mes.funcs = &mes_v12_0_funcs;
12671267
adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init;
12681268
adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini;
1269+
adev->mes.enable_legacy_queue_map = true;
12691270

12701271
adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE;
12711272

@@ -1422,9 +1423,11 @@ static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev)
14221423
mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_KIQ_PIPE);
14231424
}
14241425

1425-
r = mes_v12_0_hw_init(adev);
1426-
if (r)
1427-
goto failure;
1426+
if (adev->mes.enable_legacy_queue_map) {
1427+
r = mes_v12_0_hw_init(adev);
1428+
if (r)
1429+
goto failure;
1430+
}
14281431

14291432
return r;
14301433

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

Lines changed: 37 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1752,6 +1752,30 @@ static struct dml2_soc_bb *dm_dmub_get_vbios_bounding_box(struct amdgpu_device *
17521752
return bb;
17531753
}
17541754

1755+
static enum dmub_ips_disable_type dm_get_default_ips_mode(
1756+
struct amdgpu_device *adev)
1757+
{
1758+
/*
1759+
* On DCN35 systems with Z8 enabled, it's possible for IPS2 + Z8 to
1760+
* cause a hard hang. A fix exists for newer PMFW.
1761+
*
1762+
* As a workaround, for non-fixed PMFW, force IPS1+RCG as the deepest
1763+
* IPS state in all cases, except for s0ix and all displays off (DPMS),
1764+
* where IPS2 is allowed.
1765+
*
1766+
* When checking pmfw version, use the major and minor only.
1767+
*/
1768+
if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 5, 0) &&
1769+
(adev->pm.fw_version & 0x00FFFF00) < 0x005D6300)
1770+
return DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
1771+
1772+
if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0))
1773+
return DMUB_IPS_ENABLE;
1774+
1775+
/* ASICs older than DCN35 do not have IPSs */
1776+
return DMUB_IPS_DISABLE_ALL;
1777+
}
1778+
17551779
static int amdgpu_dm_init(struct amdgpu_device *adev)
17561780
{
17571781
struct dc_init_data init_data;
@@ -1863,7 +1887,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
18631887
if (amdgpu_dc_debug_mask & DC_DISABLE_IPS)
18641888
init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL;
18651889
else
1866-
init_data.flags.disable_ips = DMUB_IPS_ENABLE;
1890+
init_data.flags.disable_ips = dm_get_default_ips_mode(adev);
18671891

18681892
init_data.flags.disable_ips_in_vpb = 0;
18691893

@@ -4492,7 +4516,7 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
44924516
struct amdgpu_dm_backlight_caps caps;
44934517
struct dc_link *link;
44944518
u32 brightness;
4495-
bool rc;
4519+
bool rc, reallow_idle = false;
44964520

44974521
amdgpu_dm_update_backlight_caps(dm, bl_idx);
44984522
caps = dm->backlight_caps[bl_idx];
@@ -4505,6 +4529,12 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
45054529
link = (struct dc_link *)dm->backlight_link[bl_idx];
45064530

45074531
/* Change brightness based on AUX property */
4532+
mutex_lock(&dm->dc_lock);
4533+
if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) {
4534+
dc_allow_idle_optimizations(dm->dc, false);
4535+
reallow_idle = true;
4536+
}
4537+
45084538
if (caps.aux_support) {
45094539
rc = dc_link_set_backlight_level_nits(link, true, brightness,
45104540
AUX_BL_DEFAULT_TRANSITION_TIME_MS);
@@ -4516,6 +4546,11 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
45164546
DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
45174547
}
45184548

4549+
if (dm->dc->caps.ips_support && reallow_idle)
4550+
dc_allow_idle_optimizations(dm->dc, true);
4551+
4552+
mutex_unlock(&dm->dc_lock);
4553+
45194554
if (rc)
45204555
dm->actual_brightness[bl_idx] = user_brightness;
45214556
}

‎drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -811,7 +811,8 @@ static void build_synchronized_timing_groups(
811811
for (j = i + 1; j < display_config->display_config.num_streams; j++) {
812812
if (memcmp(master_timing,
813813
&display_config->display_config.stream_descriptors[j].timing,
814-
sizeof(struct dml2_timing_cfg)) == 0) {
814+
sizeof(struct dml2_timing_cfg)) == 0 &&
815+
display_config->display_config.stream_descriptors[i].output.output_encoder == display_config->display_config.stream_descriptors[j].output.output_encoder) {
815816
set_bit_in_bitfield(&pmo->scratch.pmo_dcn4.synchronized_timing_group_masks[timing_group_idx], j);
816817
set_bit_in_bitfield(&stream_mapped_mask, j);
817818
}

‎drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2266,7 +2266,8 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu,
22662266
smu_dpm_ctx->dpm_level = level;
22672267
}
22682268

2269-
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
2269+
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2270+
smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
22702271
index = fls(smu->workload_mask);
22712272
index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
22722273
workload[0] = smu->workload_setting[index];
@@ -2345,7 +2346,8 @@ static int smu_switch_power_profile(void *handle,
23452346
workload[0] = smu->workload_setting[index];
23462347
}
23472348

2348-
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
2349+
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
2350+
smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
23492351
smu_bump_power_profile_mode(smu, workload, 0);
23502352

23512353
return 0;

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