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digetxthierryreding
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memory: tegra: Consolidate registers definition into common header
The Memory Controller registers definition is sparse and duplicated, let's consolidate everything into a common place for consistency. Acked-by: Peter De Schrijver <[email protected]> Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
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4 files changed

+47
-74
lines changed

4 files changed

+47
-74
lines changed

‎drivers/memory/tegra/mc.c

Lines changed: 0 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -19,36 +19,6 @@
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2020
#include "mc.h"
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22-
#define MC_INTSTATUS 0x000
23-
24-
#define MC_INTMASK 0x004
25-
26-
#define MC_ERR_STATUS 0x08
27-
#define MC_ERR_STATUS_TYPE_SHIFT 28
28-
#define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT)
29-
#define MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT)
30-
#define MC_ERR_STATUS_READABLE (1 << 27)
31-
#define MC_ERR_STATUS_WRITABLE (1 << 26)
32-
#define MC_ERR_STATUS_NONSECURE (1 << 25)
33-
#define MC_ERR_STATUS_ADR_HI_SHIFT 20
34-
#define MC_ERR_STATUS_ADR_HI_MASK 0x3
35-
#define MC_ERR_STATUS_SECURITY (1 << 17)
36-
#define MC_ERR_STATUS_RW (1 << 16)
37-
38-
#define MC_ERR_ADR 0x0c
39-
40-
#define MC_GART_ERROR_REQ 0x30
41-
#define MC_DECERR_EMEM_OTHERS_STATUS 0x58
42-
#define MC_SECURITY_VIOLATION_STATUS 0x74
43-
44-
#define MC_EMEM_ARB_CFG 0x90
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#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0)
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#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
47-
#define MC_EMEM_ARB_MISC0 0xd8
48-
49-
#define MC_EMEM_ADR_CFG 0x54
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#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
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static const struct of_device_id tegra_mc_of_match[] = {
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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{ .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },

‎drivers/memory/tegra/mc.h

Lines changed: 47 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,37 @@
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#include <soc/tegra/mc.h>
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15+
#define MC_INTSTATUS 0x00
16+
#define MC_INTMASK 0x04
17+
#define MC_ERR_STATUS 0x08
18+
#define MC_ERR_ADR 0x0c
19+
#define MC_GART_ERROR_REQ 0x30
20+
#define MC_EMEM_ADR_CFG 0x54
21+
#define MC_DECERR_EMEM_OTHERS_STATUS 0x58
22+
#define MC_SECURITY_VIOLATION_STATUS 0x74
23+
#define MC_EMEM_ARB_CFG 0x90
24+
#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
25+
#define MC_EMEM_ARB_TIMING_RCD 0x98
26+
#define MC_EMEM_ARB_TIMING_RP 0x9c
27+
#define MC_EMEM_ARB_TIMING_RC 0xa0
28+
#define MC_EMEM_ARB_TIMING_RAS 0xa4
29+
#define MC_EMEM_ARB_TIMING_FAW 0xa8
30+
#define MC_EMEM_ARB_TIMING_RRD 0xac
31+
#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
32+
#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
33+
#define MC_EMEM_ARB_TIMING_R2R 0xb8
34+
#define MC_EMEM_ARB_TIMING_W2W 0xbc
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#define MC_EMEM_ARB_TIMING_R2W 0xc0
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#define MC_EMEM_ARB_TIMING_W2R 0xc4
37+
#define MC_EMEM_ARB_DA_TURNS 0xd0
38+
#define MC_EMEM_ARB_DA_COVERS 0xd4
39+
#define MC_EMEM_ARB_MISC0 0xd8
40+
#define MC_EMEM_ARB_MISC1 0xdc
41+
#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
42+
#define MC_EMEM_ARB_OVERRIDE 0xe8
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#define MC_TIMING_CONTROL_DBG 0xf8
44+
#define MC_TIMING_CONTROL 0xfc
45+
1546
#define MC_INT_DECERR_MTS BIT(16)
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#define MC_INT_SECERR_SEC BIT(13)
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#define MC_INT_DECERR_VPR BIT(12)
@@ -22,17 +53,28 @@
2253
#define MC_INT_INVALID_GART_PAGE BIT(7)
2354
#define MC_INT_DECERR_EMEM BIT(6)
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25-
#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
56+
#define MC_ERR_STATUS_TYPE_SHIFT 28
57+
#define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (0x6 << 28)
58+
#define MC_ERR_STATUS_TYPE_MASK (0x7 << 28)
59+
#define MC_ERR_STATUS_READABLE BIT(27)
60+
#define MC_ERR_STATUS_WRITABLE BIT(26)
61+
#define MC_ERR_STATUS_NONSECURE BIT(25)
62+
#define MC_ERR_STATUS_ADR_HI_SHIFT 20
63+
#define MC_ERR_STATUS_ADR_HI_MASK 0x3
64+
#define MC_ERR_STATUS_SECURITY BIT(17)
65+
#define MC_ERR_STATUS_RW BIT(16)
66+
67+
#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
68+
69+
#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) ((x) & 0x1ff)
70+
#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
71+
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#define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK 0x1ff
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#define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE BIT(30)
2874
#define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE BIT(31)
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30-
#define MC_EMEM_ARB_OVERRIDE 0xe8
3176
#define MC_EMEM_ARB_OVERRIDE_EACK_MASK 0x3
3277

33-
#define MC_TIMING_CONTROL_DBG 0xf8
34-
35-
#define MC_TIMING_CONTROL 0xfc
3678
#define MC_TIMING_UPDATE BIT(0)
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3880
static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset)

‎drivers/memory/tegra/tegra124.c

Lines changed: 0 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -10,26 +10,6 @@
1010

1111
#include "mc.h"
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13-
#define MC_EMEM_ARB_CFG 0x90
14-
#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
15-
#define MC_EMEM_ARB_TIMING_RCD 0x98
16-
#define MC_EMEM_ARB_TIMING_RP 0x9c
17-
#define MC_EMEM_ARB_TIMING_RC 0xa0
18-
#define MC_EMEM_ARB_TIMING_RAS 0xa4
19-
#define MC_EMEM_ARB_TIMING_FAW 0xa8
20-
#define MC_EMEM_ARB_TIMING_RRD 0xac
21-
#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
22-
#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
23-
#define MC_EMEM_ARB_TIMING_R2R 0xb8
24-
#define MC_EMEM_ARB_TIMING_W2W 0xbc
25-
#define MC_EMEM_ARB_TIMING_R2W 0xc0
26-
#define MC_EMEM_ARB_TIMING_W2R 0xc4
27-
#define MC_EMEM_ARB_DA_TURNS 0xd0
28-
#define MC_EMEM_ARB_DA_COVERS 0xd4
29-
#define MC_EMEM_ARB_MISC0 0xd8
30-
#define MC_EMEM_ARB_MISC1 0xdc
31-
#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
32-
3313
static const struct tegra_mc_client tegra124_mc_clients[] = {
3414
{
3515
.id = 0x00,

‎drivers/memory/tegra/tegra30.c

Lines changed: 0 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -10,25 +10,6 @@
1010

1111
#include "mc.h"
1212

13-
#define MC_EMEM_ARB_CFG 0x90
14-
#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
15-
#define MC_EMEM_ARB_TIMING_RCD 0x98
16-
#define MC_EMEM_ARB_TIMING_RP 0x9c
17-
#define MC_EMEM_ARB_TIMING_RC 0xa0
18-
#define MC_EMEM_ARB_TIMING_RAS 0xa4
19-
#define MC_EMEM_ARB_TIMING_FAW 0xa8
20-
#define MC_EMEM_ARB_TIMING_RRD 0xac
21-
#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
22-
#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
23-
#define MC_EMEM_ARB_TIMING_R2R 0xb8
24-
#define MC_EMEM_ARB_TIMING_W2W 0xbc
25-
#define MC_EMEM_ARB_TIMING_R2W 0xc0
26-
#define MC_EMEM_ARB_TIMING_W2R 0xc4
27-
#define MC_EMEM_ARB_DA_TURNS 0xd0
28-
#define MC_EMEM_ARB_DA_COVERS 0xd4
29-
#define MC_EMEM_ARB_MISC0 0xd8
30-
#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
31-
3213
static const unsigned long tegra30_mc_emem_regs[] = {
3314
MC_EMEM_ARB_CFG,
3415
MC_EMEM_ARB_OUTSTANDING_REQ,

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