Skip to content

Commit 14680b2

Browse files
bjorn-helgaasbjorn-helgaas
committed
Merge branch 'pci/dt-bindings'
- Add rcar-pci-host missing IOMMU properties (Geert Uytterhoeven) - Add ti,j721e-pci-host J784S4 Device ID (Siddharth Vadapalli) - Add ti,j721e-pci-host J722S compatible string (Siddharth Vadapalli) - Add ti,am65 num-viewport, phys, and phy-name properties (Jan Kiszka) - Drop cdns,cdns-pcie-host redundant msi-parent and pci-bus.yaml (Krzysztof Kozlowski) - Add mediatek,mt7621 missing reg property for child Root Ports (Krzysztof Kozlowski) - Switch bindings from pci-bus.yaml to pci-host-bridge.yaml (Krzysztof Kozlowski) - Convert fsl,layerscape host and endpoint bindings to YAML (Frank Li) - Add rcar-gen4-pci-host R-Car V4H (R8A779G0) compatible strings for both host and endpoint mode (Yoshihiro Shimoda) - Add rockchip,rk3399-pcie maxItems for ep-gpios (Krzysztof Kozlowski) * pci/dt-bindings: dt-bindings: PCI: rockchip,rk3399-pcie: Add missing maxItems to ep-gpios dt-bindings: PCI: rcar-gen4-pci-ep: Add R-Car V4H compatible dt-bindings: PCI: rcar-gen4-pci-host: Add R-Car V4H compatible dt-bindings: PCI: layerscape-pci: Convert to YAML format dt-bindings: PCI: mediatek,mt7621-pcie: Switch from deprecated pci-bus.yaml dt-bindings: PCI: host-bridges: Switch from deprecated pci-bus.yaml dt-bindings: PCI: mediatek,mt7621: Add missing child node reg dt-bindings: PCI: cdns,cdns-pcie-host: Drop redundant msi-parent and pci-bus.yaml dt-bindings: PCI: ti,am65: Fix remaining binding warnings dt-bindings: PCI: ti,j721e-pci-host: Add support for J722S SoC dt-bindings: PCI: rcar-pci-host: Add missing IOMMU properties dt-bindings: PCI: ti,j721e-pci-host: Add device-id for TI's J784S4 SoC
2 parents 12ff1ef + 52d0663 commit 14680b2

32 files changed

+333
-110
lines changed

‎Documentation/devicetree/bindings/pci/amlogic,axg-pcie.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ description:
1313
Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
1414

1515
allOf:
16-
- $ref: /schemas/pci/pci-bus.yaml#
16+
- $ref: /schemas/pci/pci-host-bridge.yaml#
1717
- $ref: /schemas/pci/snps,dw-pcie-common.yaml#
1818

1919
# We need a select here so we don't match all nodes with 'snps,dw-pcie'

‎Documentation/devicetree/bindings/pci/apple,pcie.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,7 @@ required:
8585
unevaluatedProperties: false
8686

8787
allOf:
88-
- $ref: /schemas/pci/pci-bus.yaml#
88+
- $ref: /schemas/pci/pci-host-bridge.yaml#
8989
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
9090
- if:
9191
properties:

‎Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ maintainers:
1111
- Scott Branden <[email protected]>
1212

1313
allOf:
14-
- $ref: /schemas/pci/pci-bus.yaml#
14+
- $ref: /schemas/pci/pci-host-bridge.yaml#
1515

1616
properties:
1717
compatible:

‎Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,7 @@ required:
108108
- msi-controller
109109

110110
allOf:
111-
- $ref: /schemas/pci/pci-bus.yaml#
111+
- $ref: /schemas/pci/pci-host-bridge.yaml#
112112
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
113113
- if:
114114
properties:

‎Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,6 @@ maintainers:
1010
- Tom Joseph <[email protected]>
1111

1212
allOf:
13-
- $ref: /schemas/pci/pci-bus.yaml#
1413
- $ref: cdns-pcie-host.yaml#
1514

1615
properties:
@@ -25,8 +24,6 @@ properties:
2524
- const: reg
2625
- const: cfg
2726

28-
msi-parent: true
29-
3027
required:
3128
- reg
3229
- reg-names

‎Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ maintainers:
1010
- Tom Joseph <[email protected]>
1111

1212
allOf:
13-
- $ref: /schemas/pci/pci-bus.yaml#
13+
- $ref: /schemas/pci/pci-host-bridge.yaml#
1414
- $ref: cdns-pcie.yaml#
1515

1616
properties:

‎Documentation/devicetree/bindings/pci/faraday,ftpci100.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ description: |
5151
<0x6000 0 0 4 &pci_intc 2>;
5252
5353
allOf:
54-
- $ref: /schemas/pci/pci-bus.yaml#
54+
- $ref: /schemas/pci/pci-host-bridge.yaml#
5555

5656
properties:
5757
compatible:

‎Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml

Lines changed: 102 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,102 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Freescale Layerscape PCIe Endpoint(EP) controller
8+
9+
maintainers:
10+
- Frank Li <[email protected]>
11+
12+
description:
13+
This PCIe EP controller is based on the Synopsys DesignWare PCIe IP.
14+
15+
This controller derives its clocks from the Reset Configuration Word (RCW)
16+
which is used to describe the PLL settings at the time of chip-reset.
17+
18+
Also as per the available Reference Manuals, there is no specific 'version'
19+
register available in the Freescale PCIe controller register set,
20+
which can allow determining the underlying DesignWare PCIe controller version
21+
information.
22+
23+
properties:
24+
compatible:
25+
enum:
26+
- fsl,ls2088a-pcie-ep
27+
- fsl,ls1088a-pcie-ep
28+
- fsl,ls1046a-pcie-ep
29+
- fsl,ls1028a-pcie-ep
30+
- fsl,lx2160ar2-pcie-ep
31+
32+
reg:
33+
maxItems: 2
34+
35+
reg-names:
36+
items:
37+
- const: regs
38+
- const: addr_space
39+
40+
fsl,pcie-scfg:
41+
$ref: /schemas/types.yaml#/definitions/phandle
42+
description: A phandle to the SCFG device node. The second entry is the
43+
physical PCIe controller index starting from '0'. This is used to get
44+
SCFG PEXN registers.
45+
46+
big-endian:
47+
$ref: /schemas/types.yaml#/definitions/flag
48+
description: If the PEX_LUT and PF register block is in big-endian, specify
49+
this property.
50+
51+
dma-coherent: true
52+
53+
interrupts:
54+
minItems: 1
55+
maxItems: 2
56+
57+
interrupt-names:
58+
minItems: 1
59+
maxItems: 2
60+
61+
required:
62+
- compatible
63+
- reg
64+
- reg-names
65+
66+
allOf:
67+
- if:
68+
properties:
69+
compatible:
70+
enum:
71+
- fsl,ls1028a-pcie-ep
72+
- fsl,ls1046a-pcie-ep
73+
- fsl,ls1088a-pcie-ep
74+
then:
75+
properties:
76+
interrupt-names:
77+
items:
78+
- const: pme
79+
80+
unevaluatedProperties: false
81+
82+
examples:
83+
- |
84+
#include <dt-bindings/interrupt-controller/arm-gic.h>
85+
86+
soc {
87+
#address-cells = <2>;
88+
#size-cells = <2>;
89+
90+
pcie_ep1: pcie-ep@3400000 {
91+
compatible = "fsl,ls1028a-pcie-ep";
92+
reg = <0x00 0x03400000 0x0 0x00100000
93+
0x80 0x00000000 0x8 0x00000000>;
94+
reg-names = "regs", "addr_space";
95+
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
96+
interrupt-names = "pme";
97+
num-ib-windows = <6>;
98+
num-ob-windows = <8>;
99+
status = "disabled";
100+
};
101+
};
102+
...

‎Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml

Lines changed: 167 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,167 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Freescale Layerscape PCIe Root Complex(RC) controller
8+
9+
maintainers:
10+
- Frank Li <[email protected]>
11+
12+
description:
13+
This PCIe RC controller is based on the Synopsys DesignWare PCIe IP
14+
15+
This controller derives its clocks from the Reset Configuration Word (RCW)
16+
which is used to describe the PLL settings at the time of chip-reset.
17+
18+
Also as per the available Reference Manuals, there is no specific 'version'
19+
register available in the Freescale PCIe controller register set,
20+
which can allow determining the underlying DesignWare PCIe controller version
21+
information.
22+
23+
properties:
24+
compatible:
25+
enum:
26+
- fsl,ls1021a-pcie
27+
- fsl,ls2080a-pcie
28+
- fsl,ls2085a-pcie
29+
- fsl,ls2088a-pcie
30+
- fsl,ls1088a-pcie
31+
- fsl,ls1046a-pcie
32+
- fsl,ls1043a-pcie
33+
- fsl,ls1012a-pcie
34+
- fsl,ls1028a-pcie
35+
- fsl,lx2160a-pcie
36+
37+
reg:
38+
maxItems: 2
39+
40+
reg-names:
41+
items:
42+
- const: regs
43+
- const: config
44+
45+
fsl,pcie-scfg:
46+
$ref: /schemas/types.yaml#/definitions/phandle
47+
description: A phandle to the SCFG device node. The second entry is the
48+
physical PCIe controller index starting from '0'. This is used to get
49+
SCFG PEXN registers.
50+
51+
big-endian:
52+
$ref: /schemas/types.yaml#/definitions/flag
53+
description: If the PEX_LUT and PF register block is in big-endian, specify
54+
this property.
55+
56+
dma-coherent: true
57+
58+
msi-parent: true
59+
60+
iommu-map: true
61+
62+
interrupts:
63+
minItems: 1
64+
maxItems: 2
65+
66+
interrupt-names:
67+
minItems: 1
68+
maxItems: 2
69+
70+
required:
71+
- compatible
72+
- reg
73+
- reg-names
74+
- "#address-cells"
75+
- "#size-cells"
76+
- device_type
77+
- bus-range
78+
- ranges
79+
- interrupts
80+
- interrupt-names
81+
- "#interrupt-cells"
82+
- interrupt-map-mask
83+
- interrupt-map
84+
85+
allOf:
86+
- $ref: /schemas/pci/pci-bus.yaml#
87+
88+
- if:
89+
properties:
90+
compatible:
91+
enum:
92+
- fsl,ls1028a-pcie
93+
- fsl,ls1046a-pcie
94+
- fsl,ls1043a-pcie
95+
- fsl,ls1012a-pcie
96+
then:
97+
properties:
98+
interrupts:
99+
maxItems: 2
100+
interrupt-names:
101+
items:
102+
- const: pme
103+
- const: aer
104+
105+
- if:
106+
properties:
107+
compatible:
108+
enum:
109+
- fsl,ls2080a-pcie
110+
- fsl,ls2085a-pcie
111+
- fsl,ls2088a-pcie
112+
then:
113+
properties:
114+
interrupts:
115+
maxItems: 1
116+
interrupt-names:
117+
items:
118+
- const: intr
119+
120+
- if:
121+
properties:
122+
compatible:
123+
enum:
124+
- fsl,ls1088a-pcie
125+
then:
126+
properties:
127+
interrupts:
128+
maxItems: 1
129+
interrupt-names:
130+
items:
131+
- const: aer
132+
133+
unevaluatedProperties: false
134+
135+
examples:
136+
- |
137+
#include <dt-bindings/interrupt-controller/arm-gic.h>
138+
139+
soc {
140+
#address-cells = <2>;
141+
#size-cells = <2>;
142+
143+
pcie@3400000 {
144+
compatible = "fsl,ls1088a-pcie";
145+
reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
146+
<0x20 0x00000000 0x0 0x00002000>; /* configuration space */
147+
reg-names = "regs", "config";
148+
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
149+
interrupt-names = "aer";
150+
#address-cells = <3>;
151+
#size-cells = <2>;
152+
dma-coherent;
153+
device_type = "pci";
154+
bus-range = <0x0 0xff>;
155+
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
156+
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
157+
msi-parent = <&its>;
158+
#interrupt-cells = <1>;
159+
interrupt-map-mask = <0 0 0 7>;
160+
interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
161+
<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
162+
<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
163+
<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
164+
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
165+
};
166+
};
167+
...

‎Documentation/devicetree/bindings/pci/host-generic-pci.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -116,7 +116,7 @@ required:
116116
- ranges
117117

118118
allOf:
119-
- $ref: /schemas/pci/pci-bus.yaml#
119+
- $ref: /schemas/pci/pci-host-bridge.yaml#
120120
- if:
121121
properties:
122122
compatible:

0 commit comments

Comments
 (0)