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36 | 36 | #define EFER_FFXSR (1<<_EFER_FFXSR) |
37 | 37 | #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) |
38 | 38 |
|
| 39 | +/* |
| 40 | + * Architectural memory types that are common to MTRRs, PAT, VMX MSRs, etc. |
| 41 | + * Most MSRs support/allow only a subset of memory types, but the values |
| 42 | + * themselves are common across all relevant MSRs. |
| 43 | + */ |
| 44 | +#define X86_MEMTYPE_UC 0ull /* Uncacheable, a.k.a. Strong Uncacheable */ |
| 45 | +#define X86_MEMTYPE_WC 1ull /* Write Combining */ |
| 46 | +/* RESERVED 2 */ |
| 47 | +/* RESERVED 3 */ |
| 48 | +#define X86_MEMTYPE_WT 4ull /* Write Through */ |
| 49 | +#define X86_MEMTYPE_WP 5ull /* Write Protected */ |
| 50 | +#define X86_MEMTYPE_WB 6ull /* Write Back */ |
| 51 | +#define X86_MEMTYPE_UC_MINUS 7ull /* Weak Uncacheabled (PAT only) */ |
| 52 | + |
39 | 53 | /* FRED MSRs */ |
40 | 54 | #define MSR_IA32_FRED_RSP0 0x1cc /* Level 0 stack pointer */ |
41 | 55 | #define MSR_IA32_FRED_RSP1 0x1cd /* Level 1 stack pointer */ |
|
365 | 379 |
|
366 | 380 | #define MSR_IA32_CR_PAT 0x00000277 |
367 | 381 |
|
| 382 | +#define PAT_VALUE(p0, p1, p2, p3, p4, p5, p6, p7) \ |
| 383 | + ((X86_MEMTYPE_ ## p0) | (X86_MEMTYPE_ ## p1 << 8) | \ |
| 384 | + (X86_MEMTYPE_ ## p2 << 16) | (X86_MEMTYPE_ ## p3 << 24) | \ |
| 385 | + (X86_MEMTYPE_ ## p4 << 32) | (X86_MEMTYPE_ ## p5 << 40) | \ |
| 386 | + (X86_MEMTYPE_ ## p6 << 48) | (X86_MEMTYPE_ ## p7 << 56)) |
| 387 | + |
368 | 388 | #define MSR_IA32_DEBUGCTLMSR 0x000001d9 |
369 | 389 | #define MSR_IA32_LASTBRANCHFROMIP 0x000001db |
370 | 390 | #define MSR_IA32_LASTBRANCHTOIP 0x000001dc |
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1159 | 1179 | #define MSR_IA32_VMX_VMFUNC 0x00000491 |
1160 | 1180 | #define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492 |
1161 | 1181 |
|
1162 | | -/* VMX_BASIC bits and bitmasks */ |
1163 | | -#define VMX_BASIC_VMCS_SIZE_SHIFT 32 |
1164 | | -#define VMX_BASIC_TRUE_CTLS (1ULL << 55) |
1165 | | -#define VMX_BASIC_64 0x0001000000000000LLU |
1166 | | -#define VMX_BASIC_MEM_TYPE_SHIFT 50 |
1167 | | -#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU |
1168 | | -#define VMX_BASIC_MEM_TYPE_WB 6LLU |
1169 | | -#define VMX_BASIC_INOUT 0x0040000000000000LLU |
1170 | | - |
1171 | 1182 | /* Resctrl MSRs: */ |
1172 | 1183 | /* - Intel: */ |
1173 | 1184 | #define MSR_IA32_L3_QOS_CFG 0xc81 |
|
1185 | 1196 | #define MSR_IA32_SMBA_BW_BASE 0xc0000280 |
1186 | 1197 | #define MSR_IA32_EVT_CFG_BASE 0xc0000400 |
1187 | 1198 |
|
1188 | | -/* MSR_IA32_VMX_MISC bits */ |
1189 | | -#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) |
1190 | | -#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) |
1191 | | -#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F |
1192 | | - |
1193 | 1199 | /* AMD-V MSRs */ |
1194 | 1200 | #define MSR_VM_CR 0xc0010114 |
1195 | 1201 | #define MSR_VM_IGNNE 0xc0010115 |
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