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Merge tag 'perf-tools-fixes-for-v6.12-2-2024-10-30' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools
Pull perf tools fixes from Arnaldo Carvalho de Melo: - Update more header copies with the kernel sources, including const.h, msr-index.h, arm64's cputype.h, kvm's, bits.h and unaligned.h - The return from 'write' isn't a pid, fix cut'n'paste error in 'perf trace' - Fix up the python binding build on architectures without HAVE_KVM_STAT_SUPPORT - Add some more bounds checks to augmented_raw_syscalls.bpf.c (used to collect syscall pointer arguments in 'perf trace') to make the resulting bytecode to pass the kernel BPF verifier, allowing us to go back accepting clang 12.0.1 as the minimum version required for compiling BPF sources - Add __NR_capget for x86 to fix a regression on running perf + intel PT (hw tracing) as non-root setting up the capabilities as described in https://www.kernel.org/doc/html/latest/admin-guide/perf-security.html - Fix missing syscalltbl in non-explicitly listed architectures, noticed on ARM 32-bit, that still needs a .tbl generator for the syscall id<->name tables, should be added for v6.13 - Handle 'perf test' failure when handling broken DWARF for ASM files * tag 'perf-tools-fixes-for-v6.12-2-2024-10-30' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools: perf cap: Add __NR_capget to arch/x86 unistd tools headers: Update the linux/unaligned.h copy with the kernel sources tools headers arm64: Sync arm64's cputype.h with the kernel sources tools headers: Synchronize {uapi/}linux/bits.h with the kernel sources tools arch x86: Sync the msr-index.h copy with the kernel sources perf python: Fix up the build on architectures without HAVE_KVM_STAT_SUPPORT perf test: Handle perftool-testsuite_probe failure due to broken DWARF tools headers UAPI: Sync kvm headers with the kernel sources perf trace: Fix non-listed archs in the syscalltbl routines perf build: Change the clang check back to 12.0.1 perf trace augmented_raw_syscalls: Add more checks to pass the verifier perf trace augmented_raw_syscalls: Add extra array index bounds checking to satisfy some BPF verifiers perf trace: The return from 'write' isn't a pid tools headers UAPI: Sync linux/const.h with the kernel headers
2 parents 4236f91 + a5384c4 commit 14b7d43

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tools/arch/arm64/include/asm/cputype.h

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@@ -94,6 +94,7 @@
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#define ARM_CPU_PART_NEOVERSE_V3 0xD84
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#define ARM_CPU_PART_CORTEX_X925 0xD85
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#define ARM_CPU_PART_CORTEX_A725 0xD87
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#define ARM_CPU_PART_NEOVERSE_N3 0xD8E
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#define APM_CPU_PART_XGENE 0x000
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#define APM_CPU_VAR_POTENZA 0x00
@@ -176,6 +177,7 @@
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#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
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#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
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#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
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#define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
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#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
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#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
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#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

tools/arch/x86/include/asm/msr-index.h

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@@ -36,6 +36,20 @@
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#define EFER_FFXSR (1<<_EFER_FFXSR)
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#define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS)
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/*
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* Architectural memory types that are common to MTRRs, PAT, VMX MSRs, etc.
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* Most MSRs support/allow only a subset of memory types, but the values
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* themselves are common across all relevant MSRs.
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*/
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#define X86_MEMTYPE_UC 0ull /* Uncacheable, a.k.a. Strong Uncacheable */
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#define X86_MEMTYPE_WC 1ull /* Write Combining */
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/* RESERVED 2 */
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/* RESERVED 3 */
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#define X86_MEMTYPE_WT 4ull /* Write Through */
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#define X86_MEMTYPE_WP 5ull /* Write Protected */
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#define X86_MEMTYPE_WB 6ull /* Write Back */
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#define X86_MEMTYPE_UC_MINUS 7ull /* Weak Uncacheabled (PAT only) */
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/* FRED MSRs */
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#define MSR_IA32_FRED_RSP0 0x1cc /* Level 0 stack pointer */
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#define MSR_IA32_FRED_RSP1 0x1cd /* Level 1 stack pointer */
@@ -365,6 +379,12 @@
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#define MSR_IA32_CR_PAT 0x00000277
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#define PAT_VALUE(p0, p1, p2, p3, p4, p5, p6, p7) \
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((X86_MEMTYPE_ ## p0) | (X86_MEMTYPE_ ## p1 << 8) | \
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(X86_MEMTYPE_ ## p2 << 16) | (X86_MEMTYPE_ ## p3 << 24) | \
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(X86_MEMTYPE_ ## p4 << 32) | (X86_MEMTYPE_ ## p5 << 40) | \
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(X86_MEMTYPE_ ## p6 << 48) | (X86_MEMTYPE_ ## p7 << 56))
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#define MSR_IA32_DEBUGCTLMSR 0x000001d9
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#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
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#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
@@ -1159,15 +1179,6 @@
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#define MSR_IA32_VMX_VMFUNC 0x00000491
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#define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492
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1162-
/* VMX_BASIC bits and bitmasks */
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#define VMX_BASIC_VMCS_SIZE_SHIFT 32
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#define VMX_BASIC_TRUE_CTLS (1ULL << 55)
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#define VMX_BASIC_64 0x0001000000000000LLU
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#define VMX_BASIC_MEM_TYPE_SHIFT 50
1167-
#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
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#define VMX_BASIC_MEM_TYPE_WB 6LLU
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#define VMX_BASIC_INOUT 0x0040000000000000LLU
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/* Resctrl MSRs: */
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/* - Intel: */
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#define MSR_IA32_L3_QOS_CFG 0xc81
@@ -1185,11 +1196,6 @@
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#define MSR_IA32_SMBA_BW_BASE 0xc0000280
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#define MSR_IA32_EVT_CFG_BASE 0xc0000400
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1188-
/* MSR_IA32_VMX_MISC bits */
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#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14)
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#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
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#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
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/* AMD-V MSRs */
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#define MSR_VM_CR 0xc0010114
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#define MSR_VM_IGNNE 0xc0010115

tools/arch/x86/include/uapi/asm/kvm.h

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@@ -439,6 +439,7 @@ struct kvm_sync_regs {
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#define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT (1 << 4)
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#define KVM_X86_QUIRK_FIX_HYPERCALL_INSN (1 << 5)
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#define KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS (1 << 6)
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#define KVM_X86_QUIRK_SLOT_ZAP_ALL (1 << 7)
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#define KVM_STATE_NESTED_FORMAT_VMX 0
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#define KVM_STATE_NESTED_FORMAT_SVM 1

tools/arch/x86/include/uapi/asm/unistd_32.h

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@@ -11,6 +11,9 @@
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#ifndef __NR_getpgid
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#define __NR_getpgid 132
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#endif
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#ifndef __NR_capget
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#define __NR_capget 184
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#endif
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#ifndef __NR_gettid
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#define __NR_gettid 224
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#endif

tools/arch/x86/include/uapi/asm/unistd_64.h

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@@ -11,6 +11,9 @@
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#ifndef __NR_getpgid
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#define __NR_getpgid 121
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#endif
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#ifndef __NR_capget
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#define __NR_capget 125
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#endif
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#ifndef __NR_gettid
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#define __NR_gettid 186
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#endif

tools/include/linux/bits.h

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@@ -36,4 +36,19 @@
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#define GENMASK_ULL(h, l) \
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(GENMASK_INPUT_CHECK(h, l) + __GENMASK_ULL(h, l))
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#if !defined(__ASSEMBLY__)
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/*
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* Missing asm support
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*
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* __GENMASK_U128() depends on _BIT128() which would not work
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* in the asm code, as it shifts an 'unsigned __init128' data
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* type instead of direct representation of 128 bit constants
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* such as long and unsigned long. The fundamental problem is
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* that a 128 bit constant will get silently truncated by the
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* gcc compiler.
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*/
50+
#define GENMASK_U128(h, l) \
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(GENMASK_INPUT_CHECK(h, l) + __GENMASK_U128(h, l))
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#endif
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#endif /* __LINUX_BITS_H */

tools/include/linux/unaligned.h

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@@ -9,16 +9,7 @@
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wpacked"
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#pragma GCC diagnostic ignored "-Wattributes"
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13-
#define __get_unaligned_t(type, ptr) ({ \
14-
const struct { type x; } __packed *__pptr = (typeof(__pptr))(ptr); \
15-
__pptr->x; \
16-
})
17-
18-
#define __put_unaligned_t(type, val, ptr) do { \
19-
struct { type x; } __packed *__pptr = (typeof(__pptr))(ptr); \
20-
__pptr->x = (val); \
21-
} while (0)
12+
#include <vdso/unaligned.h>
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2314
#define get_unaligned(ptr) __get_unaligned_t(typeof(*(ptr)), (ptr))
2415
#define put_unaligned(val, ptr) __put_unaligned_t(typeof(*(ptr)), (val), (ptr))

tools/include/uapi/linux/bits.h

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@@ -12,4 +12,7 @@
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(((~_ULL(0)) - (_ULL(1) << (l)) + 1) & \
1313
(~_ULL(0) >> (__BITS_PER_LONG_LONG - 1 - (h))))
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15+
#define __GENMASK_U128(h, l) \
16+
((_BIT128((h)) << 1) - (_BIT128(l)))
17+
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#endif /* _UAPI_LINUX_BITS_H */

tools/include/uapi/linux/const.h

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@@ -28,6 +28,23 @@
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#define _BITUL(x) (_UL(1) << (x))
2929
#define _BITULL(x) (_ULL(1) << (x))
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31+
#if !defined(__ASSEMBLY__)
32+
/*
33+
* Missing asm support
34+
*
35+
* __BIT128() would not work in the asm code, as it shifts an
36+
* 'unsigned __init128' data type as direct representation of
37+
* 128 bit constants is not supported in the gcc compiler, as
38+
* they get silently truncated.
39+
*
40+
* TODO: Please revisit this implementation when gcc compiler
41+
* starts representing 128 bit constants directly like long
42+
* and unsigned long etc. Subsequently drop the comment for
43+
* GENMASK_U128() which would then start supporting asm code.
44+
*/
45+
#define _BIT128(x) ((unsigned __int128)(1) << (x))
46+
#endif
47+
3148
#define __ALIGN_KERNEL(x, a) __ALIGN_KERNEL_MASK(x, (__typeof__(x))(a) - 1)
3249
#define __ALIGN_KERNEL_MASK(x, mask) (((x) + (mask)) & ~(mask))
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tools/include/vdso/unaligned.h

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@@ -0,0 +1,15 @@
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/* SPDX-License-Identifier: GPL-2.0 */
2+
#ifndef __VDSO_UNALIGNED_H
3+
#define __VDSO_UNALIGNED_H
4+
5+
#define __get_unaligned_t(type, ptr) ({ \
6+
const struct { type x; } __packed *__pptr = (typeof(__pptr))(ptr); \
7+
__pptr->x; \
8+
})
9+
10+
#define __put_unaligned_t(type, val, ptr) do { \
11+
struct { type x; } __packed *__pptr = (typeof(__pptr))(ptr); \
12+
__pptr->x = (val); \
13+
} while (0)
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15+
#endif /* __VDSO_UNALIGNED_H */

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