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anderssonandersson
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Merge branch '[email protected]' into clk-for-6.13
Merge IPQ5424 global clock controller binding through topic branch to make the constants available for both clock and DeviceTree branches.
2 parents 30eb0e7 + 03e525c commit 1539860

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‎Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml

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$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller on IPQ5332
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title: Qualcomm Global Clock & Reset Controller on IPQ5332 and IPQ5424
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maintainers:
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- Bjorn Andersson <[email protected]>
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description: |
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Qualcomm global clock control module provides the clocks, resets and power
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domains on IPQ5332.
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domains on IPQ5332 and IPQ5424.
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See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
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allOf:
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- $ref: qcom,gcc.yaml#
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See also:
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include/dt-bindings/clock/qcom,gcc-ipq5332.h
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include/dt-bindings/clock/qcom,gcc-ipq5424.h
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properties:
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compatible:
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const: qcom,ipq5332-gcc
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enum:
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- qcom,ipq5332-gcc
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- qcom,ipq5424-gcc
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clocks:
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minItems: 5
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items:
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- description: Board XO clock source
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- description: Sleep clock source
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- description: PCIE 2lane PHY pipe clock source
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- description: PCIE 2lane x1 PHY pipe clock source (For second lane)
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- description: USB PCIE wrapper pipe clock source
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- description: PCIE 2-lane PHY2 pipe clock source
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- description: PCIE 2-lane PHY3 pipe clock source
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'#power-domain-cells': false
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'#interconnect-cells':
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- compatible
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- clocks
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allOf:
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- $ref: qcom,gcc.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: qcom,ipq5332-gcc
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then:
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properties:
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clocks:
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maxItems: 5
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- if:
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properties:
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compatible:
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contains:
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const: qcom,ipq5424-gcc
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then:
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properties:
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clocks:
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minItems: 7
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maxItems: 7
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unevaluatedProperties: false
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examples:

‎include/dt-bindings/clock/qcom,ipq5424-gcc.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2018,2020 The Linux Foundation. All rights reserved.
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5424_H
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#define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5424_H
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#define GPLL0 0
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#define GPLL4 1
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#define GPLL2 2
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#define GPLL2_OUT_MAIN 3
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#define GCC_SLEEP_CLK_SRC 4
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#define GCC_APSS_DBG_CLK 5
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#define GCC_USB0_EUD_AT_CLK 6
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#define GCC_PCIE0_AXI_M_CLK_SRC 7
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#define GCC_PCIE0_AXI_M_CLK 8
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#define GCC_PCIE1_AXI_M_CLK_SRC 9
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#define GCC_PCIE1_AXI_M_CLK 10
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#define GCC_PCIE2_AXI_M_CLK_SRC 11
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#define GCC_PCIE2_AXI_M_CLK 12
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#define GCC_PCIE3_AXI_M_CLK_SRC 13
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#define GCC_PCIE3_AXI_M_CLK 14
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#define GCC_PCIE0_AXI_S_CLK_SRC 15
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#define GCC_PCIE0_AXI_S_BRIDGE_CLK 16
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#define GCC_PCIE0_AXI_S_CLK 17
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#define GCC_PCIE1_AXI_S_CLK_SRC 18
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#define GCC_PCIE1_AXI_S_BRIDGE_CLK 19
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#define GCC_PCIE1_AXI_S_CLK 20
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#define GCC_PCIE2_AXI_S_CLK_SRC 21
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#define GCC_PCIE2_AXI_S_BRIDGE_CLK 22
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#define GCC_PCIE2_AXI_S_CLK 23
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#define GCC_PCIE3_AXI_S_CLK_SRC 24
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#define GCC_PCIE3_AXI_S_BRIDGE_CLK 25
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#define GCC_PCIE3_AXI_S_CLK 26
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#define GCC_PCIE0_PIPE_CLK_SRC 27
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#define GCC_PCIE0_PIPE_CLK 28
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#define GCC_PCIE1_PIPE_CLK_SRC 29
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#define GCC_PCIE1_PIPE_CLK 30
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#define GCC_PCIE2_PIPE_CLK_SRC 31
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#define GCC_PCIE2_PIPE_CLK 32
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#define GCC_PCIE3_PIPE_CLK_SRC 33
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#define GCC_PCIE3_PIPE_CLK 34
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#define GCC_PCIE_AUX_CLK_SRC 35
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#define GCC_PCIE0_AUX_CLK 36
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#define GCC_PCIE1_AUX_CLK 37
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#define GCC_PCIE2_AUX_CLK 38
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#define GCC_PCIE3_AUX_CLK 39
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#define GCC_PCIE0_AHB_CLK 40
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#define GCC_PCIE1_AHB_CLK 41
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#define GCC_PCIE2_AHB_CLK 42
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#define GCC_PCIE3_AHB_CLK 43
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#define GCC_USB0_AUX_CLK_SRC 44
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#define GCC_USB0_AUX_CLK 45
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#define GCC_USB0_MASTER_CLK 46
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#define GCC_USB0_MOCK_UTMI_CLK_SRC 47
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#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 48
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#define GCC_USB0_MOCK_UTMI_CLK 49
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#define GCC_USB0_PIPE_CLK_SRC 50
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#define GCC_USB0_PIPE_CLK 51
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#define GCC_USB0_PHY_CFG_AHB_CLK 52
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#define GCC_USB0_SLEEP_CLK 53
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#define GCC_SDCC1_APPS_CLK_SRC 54
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#define GCC_SDCC1_APPS_CLK 55
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#define GCC_SDCC1_ICE_CORE_CLK_SRC 56
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#define GCC_SDCC1_ICE_CORE_CLK 57
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#define GCC_SDCC1_AHB_CLK 58
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#define GCC_PCNOC_BFDCD_CLK_SRC 59
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#define GCC_NSSCFG_CLK 60
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#define GCC_NSSNOC_NSSCC_CLK 61
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#define GCC_NSSCC_CLK 62
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#define GCC_NSSNOC_PCNOC_1_CLK 63
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#define GCC_QPIC_AHB_CLK 64
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#define GCC_QPIC_CLK 65
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#define GCC_MDIO_AHB_CLK 66
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#define GCC_PRNG_AHB_CLK 67
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#define GCC_UNIPHY0_AHB_CLK 68
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#define GCC_UNIPHY1_AHB_CLK 69
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#define GCC_UNIPHY2_AHB_CLK 70
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#define GCC_CMN_12GPLL_AHB_CLK 71
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#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 72
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#define GCC_NSSNOC_SNOC_CLK 73
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#define GCC_NSSNOC_SNOC_1_CLK 74
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#define GCC_WCSS_AHB_CLK_SRC 75
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#define GCC_QDSS_AT_CLK_SRC 76
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#define GCC_NSSNOC_ATB_CLK 77
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#define GCC_QDSS_AT_CLK 78
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#define GCC_QDSS_TSCTR_CLK_SRC 79
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#define GCC_NSS_TS_CLK 80
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#define GCC_QPIC_IO_MACRO_CLK_SRC 81
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#define GCC_QPIC_IO_MACRO_CLK 82
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#define GCC_LPASS_AXIM_CLK_SRC 83
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#define GCC_LPASS_CORE_AXIM_CLK 84
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#define GCC_LPASS_SWAY_CLK_SRC 85
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#define GCC_LPASS_SWAY_CLK 86
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#define GCC_CNOC_LPASS_CFG_CLK 87
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#define GCC_SNOC_LPASS_CLK 88
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#define GCC_ADSS_PWM_CLK_SRC 89
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#define GCC_ADSS_PWM_CLK 90
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#define GCC_XO_CLK_SRC 91
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#define GCC_NSSNOC_XO_DCD_CLK 92
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#define GCC_NSSNOC_QOSGEN_REF_CLK 93
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#define GCC_NSSNOC_TIMEOUT_REF_CLK 94
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#define GCC_UNIPHY0_SYS_CLK 95
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#define GCC_UNIPHY1_SYS_CLK 96
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#define GCC_UNIPHY2_SYS_CLK 97
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#define GCC_CMN_12GPLL_SYS_CLK 98
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#define GCC_UNIPHY_SYS_CLK_SRC 99
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#define GCC_NSS_TS_CLK_SRC 100
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#define GCC_ANOC_PCIE0_1LANE_M_CLK 101
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#define GCC_ANOC_PCIE1_1LANE_M_CLK 102
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#define GCC_ANOC_PCIE2_2LANE_M_CLK 103
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#define GCC_ANOC_PCIE3_2LANE_M_CLK 104
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#define GCC_CNOC_PCIE0_1LANE_S_CLK 105
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#define GCC_CNOC_PCIE1_1LANE_S_CLK 106
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#define GCC_CNOC_PCIE2_2LANE_S_CLK 107
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#define GCC_CNOC_PCIE3_2LANE_S_CLK 108
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#define GCC_CNOC_USB_CLK 109
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#define GCC_CNOC_WCSS_AHB_CLK 110
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#define GCC_QUPV3_AHB_MST_CLK 111
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#define GCC_QUPV3_AHB_SLV_CLK 112
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#define GCC_QUPV3_I2C0_CLK 113
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#define GCC_QUPV3_I2C1_CLK 114
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#define GCC_QUPV3_SPI0_CLK 115
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#define GCC_QUPV3_SPI1_CLK 116
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#define GCC_QUPV3_UART0_CLK 117
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#define GCC_QUPV3_UART1_CLK 118
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#define GCC_QPIC_CLK_SRC 119
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#define GCC_QUPV3_I2C0_CLK_SRC 120
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#define GCC_QUPV3_I2C1_CLK_SRC 121
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#define GCC_QUPV3_I2C0_DIV_CLK_SRC 122
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#define GCC_QUPV3_I2C1_DIV_CLK_SRC 123
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#define GCC_QUPV3_SPI0_CLK_SRC 124
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#define GCC_QUPV3_SPI1_CLK_SRC 125
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#define GCC_QUPV3_UART0_CLK_SRC 126
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#define GCC_QUPV3_UART1_CLK_SRC 127
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#define GCC_USB1_MASTER_CLK 128
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#define GCC_USB1_MOCK_UTMI_CLK_SRC 129
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#define GCC_USB1_MOCK_UTMI_DIV_CLK_SRC 130
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#define GCC_USB1_MOCK_UTMI_CLK 131
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#define GCC_USB1_SLEEP_CLK 132
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#define GCC_USB1_PHY_CFG_AHB_CLK 133
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#define GCC_USB0_MASTER_CLK_SRC 134
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#define GCC_QDSS_DAP_CLK 135
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#define GCC_PCIE0_RCHNG_CLK_SRC 136
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#define GCC_PCIE0_RCHNG_CLK 137
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#define GCC_PCIE1_RCHNG_CLK_SRC 138
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#define GCC_PCIE1_RCHNG_CLK 139
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#define GCC_PCIE2_RCHNG_CLK_SRC 140
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#define GCC_PCIE2_RCHNG_CLK 141
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#define GCC_PCIE3_RCHNG_CLK_SRC 142
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#define GCC_PCIE3_RCHNG_CLK 143
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#define GCC_IM_SLEEP_CLK 144
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#endif

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