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Merge tag 'drm-intel-gt-next-2023-02-01' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
Driver Changes: Fixes/improvements/new stuff: - Fix bcs default context on Meteorlake (Lucas De Marchi) - GAM registers don't need to be re-applied on engine resets (Matt Roper) - Correct implementation of Wa_18018781329 (Matt Roper) - Avoid potential vm use-after-free (Rob Clark) - GuC error capture fixes (John Harrison) - Fix potential bit_17 double-free (Rob Clark) - Don't complain about missing regs on MTL (John Harrison) Future platform enablement: - Convert PSS_MODE2 to multicast register (Gustavo Sousa) - Move/adjust register definitions related to Wa_22011450934 (Matt Roper) - Move LSC_CHICKEN_BIT* workarounds to correct function (Gustavo Sousa) - Document where to implement register workarounds (Gustavo Sousa) - Use uabi engines for the default engine map (Tvrtko Ursulin) - Flush all tiles on test exit (Tvrtko Ursulin) - Annotate a couple more workaround registers as MCR (Matt Roper) Driver refactors: - Add and use GuC oriented print macros (Michal Wajdeczko) Miscellaneous: - Fix intel_selftest_modify_policy argument types (Arnd Bergmann) Backmerges: Merge drm/drm-next into drm-intel-gt-next (for conflict resolution) (Tvrtko Ursulin) Signed-off-by: Dave Airlie <[email protected]> From: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/Y9pOsq7VKnq7rgnW@tursulin-desk
2 parents 535cd71 + 003e11e commit 15a5744

26 files changed

+489
-339
lines changed

‎drivers/gpu/drm/i915/gem/i915_gem_context.c

Lines changed: 15 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1096,24 +1096,23 @@ static struct i915_gem_engines *alloc_engines(unsigned int count)
10961096
static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx,
10971097
struct intel_sseu rcs_sseu)
10981098
{
1099-
const struct intel_gt *gt = to_gt(ctx->i915);
1099+
const unsigned int max = I915_NUM_ENGINES;
11001100
struct intel_engine_cs *engine;
11011101
struct i915_gem_engines *e, *err;
1102-
enum intel_engine_id id;
11031102

1104-
e = alloc_engines(I915_NUM_ENGINES);
1103+
e = alloc_engines(max);
11051104
if (!e)
11061105
return ERR_PTR(-ENOMEM);
11071106

1108-
for_each_engine(engine, gt, id) {
1107+
for_each_uabi_engine(engine, ctx->i915) {
11091108
struct intel_context *ce;
11101109
struct intel_sseu sseu = {};
11111110
int ret;
11121111

11131112
if (engine->legacy_idx == INVALID_ENGINE)
11141113
continue;
11151114

1116-
GEM_BUG_ON(engine->legacy_idx >= I915_NUM_ENGINES);
1115+
GEM_BUG_ON(engine->legacy_idx >= max);
11171116
GEM_BUG_ON(e->engines[engine->legacy_idx]);
11181117

11191118
ce = intel_context_create(engine);
@@ -1861,11 +1860,19 @@ static int get_ppgtt(struct drm_i915_file_private *file_priv,
18611860
vm = ctx->vm;
18621861
GEM_BUG_ON(!vm);
18631862

1863+
/*
1864+
* Get a reference for the allocated handle. Once the handle is
1865+
* visible in the vm_xa table, userspace could try to close it
1866+
* from under our feet, so we need to hold the extra reference
1867+
* first.
1868+
*/
1869+
i915_vm_get(vm);
1870+
18641871
err = xa_alloc(&file_priv->vm_xa, &id, vm, xa_limit_32b, GFP_KERNEL);
1865-
if (err)
1872+
if (err) {
1873+
i915_vm_put(vm);
18661874
return err;
1867-
1868-
i915_vm_get(vm);
1875+
}
18691876

18701877
GEM_BUG_ON(id == 0); /* reserved for invalid/unassigned ppgtt */
18711878
args->value = id;

‎drivers/gpu/drm/i915/gem/i915_gem_tiling.c

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -305,10 +305,6 @@ i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
305305
spin_unlock(&obj->vma.lock);
306306

307307
obj->tiling_and_stride = tiling | stride;
308-
i915_gem_object_unlock(obj);
309-
310-
/* Force the fence to be reacquired for GTT access */
311-
i915_gem_object_release_mmap_gtt(obj);
312308

313309
/* Try to preallocate memory required to save swizzling on put-pages */
314310
if (i915_gem_object_needs_bit17_swizzle(obj)) {
@@ -321,6 +317,11 @@ i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
321317
obj->bit_17 = NULL;
322318
}
323319

320+
i915_gem_object_unlock(obj);
321+
322+
/* Force the fence to be reacquired for GTT access */
323+
i915_gem_object_release_mmap_gtt(obj);
324+
324325
return 0;
325326
}
326327

‎drivers/gpu/drm/i915/gt/intel_context.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -528,7 +528,7 @@ struct i915_request *intel_context_create_request(struct intel_context *ce)
528528
return rq;
529529
}
530530

531-
struct i915_request *intel_context_find_active_request(struct intel_context *ce)
531+
struct i915_request *intel_context_get_active_request(struct intel_context *ce)
532532
{
533533
struct intel_context *parent = intel_context_to_parent(ce);
534534
struct i915_request *rq, *active = NULL;
@@ -552,6 +552,8 @@ struct i915_request *intel_context_find_active_request(struct intel_context *ce)
552552

553553
active = rq;
554554
}
555+
if (active)
556+
active = i915_request_get_rcu(active);
555557
spin_unlock_irqrestore(&parent->guc_state.lock, flags);
556558

557559
return active;

‎drivers/gpu/drm/i915/gt/intel_context.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -268,8 +268,7 @@ int intel_context_prepare_remote_request(struct intel_context *ce,
268268

269269
struct i915_request *intel_context_create_request(struct intel_context *ce);
270270

271-
struct i915_request *
272-
intel_context_find_active_request(struct intel_context *ce);
271+
struct i915_request *intel_context_get_active_request(struct intel_context *ce);
273272

274273
static inline bool intel_context_is_barrier(const struct intel_context *ce)
275274
{

‎drivers/gpu/drm/i915/gt/intel_engine.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -250,8 +250,8 @@ void intel_engine_dump_active_requests(struct list_head *requests,
250250
ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine,
251251
ktime_t *now);
252252

253-
struct i915_request *
254-
intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine);
253+
void intel_engine_get_hung_entity(struct intel_engine_cs *engine,
254+
struct intel_context **ce, struct i915_request **rq);
255255

256256
u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
257257
struct intel_context *

‎drivers/gpu/drm/i915/gt/intel_engine_cs.c

Lines changed: 40 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -1584,11 +1584,8 @@ static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
15841584
};
15851585
u32 val;
15861586

1587-
if (!_reg[engine->id].reg) {
1588-
drm_err(&engine->i915->drm,
1589-
"MSG IDLE undefined for engine id %u\n", engine->id);
1587+
if (!_reg[engine->id].reg)
15901588
return 0;
1591-
}
15921589

15931590
val = intel_uncore_read(engine->uncore, _reg[engine->id]);
15941591

@@ -2114,17 +2111,6 @@ static void print_request_ring(struct drm_printer *m, struct i915_request *rq)
21142111
}
21152112
}
21162113

2117-
static unsigned long list_count(struct list_head *list)
2118-
{
2119-
struct list_head *pos;
2120-
unsigned long count = 0;
2121-
2122-
list_for_each(pos, list)
2123-
count++;
2124-
2125-
return count;
2126-
}
2127-
21282114
static unsigned long read_ul(void *p, size_t x)
21292115
{
21302116
return *(unsigned long *)(p + x);
@@ -2216,11 +2202,11 @@ void intel_engine_dump_active_requests(struct list_head *requests,
22162202
}
22172203
}
22182204

2219-
static void engine_dump_active_requests(struct intel_engine_cs *engine, struct drm_printer *m)
2205+
static void engine_dump_active_requests(struct intel_engine_cs *engine,
2206+
struct drm_printer *m)
22202207
{
2208+
struct intel_context *hung_ce = NULL;
22212209
struct i915_request *hung_rq = NULL;
2222-
struct intel_context *ce;
2223-
bool guc;
22242210

22252211
/*
22262212
* No need for an engine->irq_seqno_barrier() before the seqno reads.
@@ -2229,27 +2215,22 @@ static void engine_dump_active_requests(struct intel_engine_cs *engine, struct d
22292215
* But the intention here is just to report an instantaneous snapshot
22302216
* so that's fine.
22312217
*/
2232-
lockdep_assert_held(&engine->sched_engine->lock);
2218+
intel_engine_get_hung_entity(engine, &hung_ce, &hung_rq);
22332219

22342220
drm_printf(m, "\tRequests:\n");
22352221

2236-
guc = intel_uc_uses_guc_submission(&engine->gt->uc);
2237-
if (guc) {
2238-
ce = intel_engine_get_hung_context(engine);
2239-
if (ce)
2240-
hung_rq = intel_context_find_active_request(ce);
2241-
} else {
2242-
hung_rq = intel_engine_execlist_find_hung_request(engine);
2243-
}
2244-
22452222
if (hung_rq)
22462223
engine_dump_request(hung_rq, m, "\t\thung");
2224+
else if (hung_ce)
2225+
drm_printf(m, "\t\tGot hung ce but no hung rq!\n");
22472226

2248-
if (guc)
2227+
if (intel_uc_uses_guc_submission(&engine->gt->uc))
22492228
intel_guc_dump_active_requests(engine, hung_rq, m);
22502229
else
2251-
intel_engine_dump_active_requests(&engine->sched_engine->requests,
2252-
hung_rq, m);
2230+
intel_execlists_dump_active_requests(engine, hung_rq, m);
2231+
2232+
if (hung_rq)
2233+
i915_request_put(hung_rq);
22532234
}
22542235

22552236
void intel_engine_dump(struct intel_engine_cs *engine,
@@ -2259,7 +2240,6 @@ void intel_engine_dump(struct intel_engine_cs *engine,
22592240
struct i915_gpu_error * const error = &engine->i915->gpu_error;
22602241
struct i915_request *rq;
22612242
intel_wakeref_t wakeref;
2262-
unsigned long flags;
22632243
ktime_t dummy;
22642244

22652245
if (header) {
@@ -2296,13 +2276,8 @@ void intel_engine_dump(struct intel_engine_cs *engine,
22962276
i915_reset_count(error));
22972277
print_properties(engine, m);
22982278

2299-
spin_lock_irqsave(&engine->sched_engine->lock, flags);
23002279
engine_dump_active_requests(engine, m);
23012280

2302-
drm_printf(m, "\tOn hold?: %lu\n",
2303-
list_count(&engine->sched_engine->hold));
2304-
spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
2305-
23062281
drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base);
23072282
wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm);
23082283
if (wakeref) {
@@ -2348,8 +2323,7 @@ intel_engine_create_virtual(struct intel_engine_cs **siblings,
23482323
return siblings[0]->cops->create_virtual(siblings, count, flags);
23492324
}
23502325

2351-
struct i915_request *
2352-
intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine)
2326+
static struct i915_request *engine_execlist_find_hung_request(struct intel_engine_cs *engine)
23532327
{
23542328
struct i915_request *request, *active = NULL;
23552329

@@ -2401,6 +2375,33 @@ intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine)
24012375
return active;
24022376
}
24032377

2378+
void intel_engine_get_hung_entity(struct intel_engine_cs *engine,
2379+
struct intel_context **ce, struct i915_request **rq)
2380+
{
2381+
unsigned long flags;
2382+
2383+
*ce = intel_engine_get_hung_context(engine);
2384+
if (*ce) {
2385+
intel_engine_clear_hung_context(engine);
2386+
2387+
*rq = intel_context_get_active_request(*ce);
2388+
return;
2389+
}
2390+
2391+
/*
2392+
* Getting here with GuC enabled means it is a forced error capture
2393+
* with no actual hang. So, no need to attempt the execlist search.
2394+
*/
2395+
if (intel_uc_uses_guc_submission(&engine->gt->uc))
2396+
return;
2397+
2398+
spin_lock_irqsave(&engine->sched_engine->lock, flags);
2399+
*rq = engine_execlist_find_hung_request(engine);
2400+
if (*rq)
2401+
*rq = i915_request_get_rcu(*rq);
2402+
spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
2403+
}
2404+
24042405
void xehp_enable_ccs_engines(struct intel_engine_cs *engine)
24052406
{
24062407
/*

‎drivers/gpu/drm/i915/gt/intel_engine_regs.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,7 @@
8181
#define RING_EIR(base) _MMIO((base) + 0xb0)
8282
#define RING_EMR(base) _MMIO((base) + 0xb4)
8383
#define RING_ESR(base) _MMIO((base) + 0xb8)
84+
#define GEN12_STATE_ACK_DEBUG(base) _MMIO((base) + 0xbc)
8485
#define RING_INSTPM(base) _MMIO((base) + 0xc0)
8586
#define RING_CMD_CCTL(base) _MMIO((base) + 0xc4)
8687
#define ACTHD(base) _MMIO((base) + 0xc8)

‎drivers/gpu/drm/i915/gt/intel_execlists_submission.c

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4150,6 +4150,33 @@ void intel_execlists_show_requests(struct intel_engine_cs *engine,
41504150
spin_unlock_irqrestore(&sched_engine->lock, flags);
41514151
}
41524152

4153+
static unsigned long list_count(struct list_head *list)
4154+
{
4155+
struct list_head *pos;
4156+
unsigned long count = 0;
4157+
4158+
list_for_each(pos, list)
4159+
count++;
4160+
4161+
return count;
4162+
}
4163+
4164+
void intel_execlists_dump_active_requests(struct intel_engine_cs *engine,
4165+
struct i915_request *hung_rq,
4166+
struct drm_printer *m)
4167+
{
4168+
unsigned long flags;
4169+
4170+
spin_lock_irqsave(&engine->sched_engine->lock, flags);
4171+
4172+
intel_engine_dump_active_requests(&engine->sched_engine->requests, hung_rq, m);
4173+
4174+
drm_printf(m, "\tOn hold?: %lu\n",
4175+
list_count(&engine->sched_engine->hold));
4176+
4177+
spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
4178+
}
4179+
41534180
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
41544181
#include "selftest_execlists.c"
41554182
#endif

‎drivers/gpu/drm/i915/gt/intel_execlists_submission.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,10 @@ void intel_execlists_show_requests(struct intel_engine_cs *engine,
3232
int indent),
3333
unsigned int max);
3434

35+
void intel_execlists_dump_active_requests(struct intel_engine_cs *engine,
36+
struct i915_request *hung_rq,
37+
struct drm_printer *m);
38+
3539
bool
3640
intel_engine_in_execlists_submission_mode(const struct intel_engine_cs *engine);
3741

‎drivers/gpu/drm/i915/gt/intel_gt_regs.h

Lines changed: 12 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -407,6 +407,8 @@
407407
#define GEN9_WM_CHICKEN3 _MMIO(0x5588)
408408
#define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
409409

410+
#define XEHP_CULLBIT1 MCR_REG(0x6100)
411+
410412
#define CHICKEN_RASTER_1 MCR_REG(0x6204)
411413
#define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8)
412414

@@ -457,10 +459,12 @@
457459
#define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13)
458460
#define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE REG_BIT(3)
459461

462+
#define XEHP_CULLBIT2 MCR_REG(0x7030)
463+
460464
#define GEN8_L3CNTLREG _MMIO(0x7034)
461465
#define GEN8_ERRDETBCTRL (1 << 9)
462466

463-
#define PSS_MODE2 _MMIO(0x703c)
467+
#define XEHP_PSS_MODE2 MCR_REG(0x703c)
464468
#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5)
465469

466470
#define GEN7_SC_INSTDONE _MMIO(0x7100)
@@ -1096,16 +1100,19 @@
10961100
#define XEHP_MERT_MOD_CTRL MCR_REG(0xcf28)
10971101
#define RENDER_MOD_CTRL MCR_REG(0xcf2c)
10981102
#define COMP_MOD_CTRL MCR_REG(0xcf30)
1099-
#define VDBX_MOD_CTRL MCR_REG(0xcf34)
1100-
#define VEBX_MOD_CTRL MCR_REG(0xcf38)
1103+
#define XELPMP_GSC_MOD_CTRL _MMIO(0xcf30) /* media GT only */
1104+
#define XEHP_VDBX_MOD_CTRL MCR_REG(0xcf34)
1105+
#define XELPMP_VDBX_MOD_CTRL _MMIO(0xcf34)
1106+
#define XEHP_VEBX_MOD_CTRL MCR_REG(0xcf38)
1107+
#define XELPMP_VEBX_MOD_CTRL _MMIO(0xcf38)
11011108
#define FORCE_MISS_FTLB REG_BIT(3)
11021109

1103-
#define GEN12_GAMSTLB_CTRL _MMIO(0xcf4c)
1110+
#define XEHP_GAMSTLB_CTRL MCR_REG(0xcf4c)
11041111
#define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12)
11051112
#define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11)
11061113
#define TAG_BLOCK_CLKGATE_DIS REG_BIT(7)
11071114

1108-
#define GEN12_GAMCNTRL_CTRL _MMIO(0xcf54)
1115+
#define XEHP_GAMCNTRL_CTRL MCR_REG(0xcf54)
11091116
#define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12)
11101117
#define GLOBAL_INVALIDATION_MODE REG_BIT(2)
11111118

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