Skip to content

Commit 16c9147

Browse files
cyyselfdlan17
authored andcommitted
dt-bindings: riscv: Add SpacemiT X60 compatibles
The X60 is RISC-V CPU cores from SpacemiT and currently used in their K1 SoC. Link: https://www.spacemit.com/en/spacemit-x60-core/ Signed-off-by: Yangyu Chen <[email protected]> Acked-by: Conor Dooley <[email protected]> Acked-by: Palmer Dabbelt <[email protected]> Signed-off-by: Yixun Lan <[email protected]>
1 parent 6055c76 commit 16c9147

File tree

1 file changed

+1
-0
lines changed
  • Documentation/devicetree/bindings/riscv

1 file changed

+1
-0
lines changed

Documentation/devicetree/bindings/riscv/cpus.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,7 @@ properties:
4646
- sifive,u7
4747
- sifive,u74
4848
- sifive,u74-mc
49+
- spacemit,x60
4950
- thead,c906
5051
- thead,c908
5152
- thead,c910

0 commit comments

Comments
 (0)