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91 | 91 | /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
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92 | 92 | #define ESDHC_TUNING_START_TAP_DEFAULT 0x1
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93 | 93 | #define ESDHC_TUNING_START_TAP_MASK 0x7f
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| 94 | +#define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE (1 << 7) |
94 | 95 | #define ESDHC_TUNING_STEP_MASK 0x00070000
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95 | 96 | #define ESDHC_TUNING_STEP_SHIFT 16
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96 | 97 |
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@@ -1316,6 +1317,18 @@ static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
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1316 | 1317 | tmp |= imx_data->boarddata.tuning_step
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1317 | 1318 | << ESDHC_TUNING_STEP_SHIFT;
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1318 | 1319 | }
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| 1320 | + |
| 1321 | + /* Disable the CMD CRC check for tuning, if not, need to |
| 1322 | + * add some delay after every tuning command, because |
| 1323 | + * hardware standard tuning logic will directly go to next |
| 1324 | + * step once it detect the CMD CRC error, will not wait for |
| 1325 | + * the card side to finally send out the tuning data, trigger |
| 1326 | + * the buffer read ready interrupt immediately. If usdhc send |
| 1327 | + * the next tuning command some eMMC card will stuck, can't |
| 1328 | + * response, block the tuning procedure or the first command |
| 1329 | + * after the whole tuning procedure always can't get any response. |
| 1330 | + */ |
| 1331 | + tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE; |
1319 | 1332 | writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
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1320 | 1333 | } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
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1321 | 1334 | /*
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@@ -1660,8 +1673,6 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
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1660 | 1673 | if (err)
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1661 | 1674 | goto disable_ahb_clk;
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1662 | 1675 |
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1663 |
| - host->tuning_delay = 1; |
1664 |
| - |
1665 | 1676 | sdhci_esdhc_imx_hwinit(host);
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1666 | 1677 |
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1667 | 1678 | err = sdhci_add_host(host);
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