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drm/panel: visionox-vtdr6130: switch to mipi_dsi wrapped functions
Make usage of the new _multi() mipi_dsi functions instead of the deprecated macros, improving error handling and printing. bloat-o-meter gives a 12% gain on arm64: Function old new delta visionox_vtdr6130_unprepare 208 204 -4 visionox_vtdr6130_prepare 1192 896 -296 Total: Before=2348, After=2048, chg -12.78% Reviewed-by: Douglas Anderson <[email protected]> Link: https://lore.kernel.org/r/20240828-topic-sm8x50-upstream-vtdr6130-multi-v1-1-0cae20d4c55d@linaro.org Signed-off-by: Neil Armstrong <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20240828-topic-sm8x50-upstream-vtdr6130-multi-v1-1-0cae20d4c55d@linaro.org
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‎drivers/gpu/drm/panel/panel-visionox-vtdr6130.c

Lines changed: 82 additions & 104 deletions
Original file line numberDiff line numberDiff line change
@@ -40,120 +40,103 @@ static void visionox_vtdr6130_reset(struct visionox_vtdr6130 *ctx)
4040
static int visionox_vtdr6130_on(struct visionox_vtdr6130 *ctx)
4141
{
4242
struct mipi_dsi_device *dsi = ctx->dsi;
43-
struct device *dev = &dsi->dev;
44-
int ret;
43+
struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
4544

4645
dsi->mode_flags |= MIPI_DSI_MODE_LPM;
4746

48-
ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
49-
if (ret)
50-
return ret;
51-
52-
mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x20);
53-
mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, 0x00, 0x00);
54-
mipi_dsi_dcs_write_seq(dsi, 0x59, 0x09);
55-
mipi_dsi_dcs_write_seq(dsi, 0x6c, 0x01);
56-
mipi_dsi_dcs_write_seq(dsi, 0x6d, 0x00);
57-
mipi_dsi_dcs_write_seq(dsi, 0x6f, 0x01);
58-
mipi_dsi_dcs_write_seq(dsi, 0x70,
59-
0x12, 0x00, 0x00, 0xab, 0x30, 0x80, 0x09, 0x60, 0x04,
60-
0x38, 0x00, 0x28, 0x02, 0x1c, 0x02, 0x1c, 0x02, 0x00,
61-
0x02, 0x0e, 0x00, 0x20, 0x03, 0xdd, 0x00, 0x07, 0x00,
62-
0x0c, 0x02, 0x77, 0x02, 0x8b, 0x18, 0x00, 0x10, 0xf0,
63-
0x07, 0x10, 0x20, 0x00, 0x06, 0x0f, 0x0f, 0x33, 0x0e,
64-
0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77,
65-
0x79, 0x7b, 0x7d, 0x7e, 0x02, 0x02, 0x22, 0x00, 0x2a,
66-
0x40, 0x2a, 0xbe, 0x3a, 0xfc, 0x3a, 0xfa, 0x3a, 0xf8,
67-
0x3b, 0x38, 0x3b, 0x78, 0x3b, 0xb6, 0x4b, 0xb6, 0x4b,
68-
0xf4, 0x4b, 0xf4, 0x6c, 0x34, 0x84, 0x74, 0x00, 0x00,
69-
0x00, 0x00, 0x00, 0x00);
70-
mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xaa, 0x10);
71-
mipi_dsi_dcs_write_seq(dsi, 0xb1,
72-
0x01, 0x38, 0x00, 0x14, 0x00, 0x1c, 0x00, 0x01, 0x66,
73-
0x00, 0x14, 0x00, 0x14, 0x00, 0x01, 0x66, 0x00, 0x14,
74-
0x05, 0xcc, 0x00);
75-
mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xaa, 0x13);
76-
mipi_dsi_dcs_write_seq(dsi, 0xce,
77-
0x09, 0x11, 0x09, 0x11, 0x08, 0xc1, 0x07, 0xfa, 0x05,
78-
0xa4, 0x00, 0x3c, 0x00, 0x34, 0x00, 0x24, 0x00, 0x0c,
79-
0x00, 0x0c, 0x04, 0x00, 0x35);
80-
mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xaa, 0x14);
81-
mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x03, 0x33);
82-
mipi_dsi_dcs_write_seq(dsi, 0xb4,
83-
0x00, 0x33, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00,
84-
0x3e, 0x00, 0x00);
85-
mipi_dsi_dcs_write_seq(dsi, 0xb5,
86-
0x00, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x06, 0x01);
87-
mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x00, 0x00, 0x08, 0x09, 0x09, 0x09);
88-
mipi_dsi_dcs_write_seq(dsi, 0xbc,
89-
0x10, 0x00, 0x00, 0x06, 0x11, 0x09, 0x3b, 0x09, 0x47,
90-
0x09, 0x47, 0x00);
91-
mipi_dsi_dcs_write_seq(dsi, 0xbe,
92-
0x10, 0x10, 0x00, 0x08, 0x22, 0x09, 0x19, 0x09, 0x25,
93-
0x09, 0x25, 0x00);
94-
mipi_dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x80);
95-
mipi_dsi_dcs_write_seq(dsi, 0x65, 0x14);
96-
mipi_dsi_dcs_write_seq(dsi, 0xfa, 0x08, 0x08, 0x08);
97-
mipi_dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x81);
98-
mipi_dsi_dcs_write_seq(dsi, 0x65, 0x05);
99-
mipi_dsi_dcs_write_seq(dsi, 0xf3, 0x0f);
100-
mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xaa, 0x00);
101-
mipi_dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x82);
102-
mipi_dsi_dcs_write_seq(dsi, 0xf9, 0x00);
103-
mipi_dsi_dcs_write_seq(dsi, 0xff, 0x51, 0x83);
104-
mipi_dsi_dcs_write_seq(dsi, 0x65, 0x04);
105-
mipi_dsi_dcs_write_seq(dsi, 0xf8, 0x00);
106-
mipi_dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x00);
107-
mipi_dsi_dcs_write_seq(dsi, 0x65, 0x01);
108-
mipi_dsi_dcs_write_seq(dsi, 0xf4, 0x9a);
109-
mipi_dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x00);
110-
111-
ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
112-
if (ret < 0) {
113-
dev_err(dev, "Failed to exit sleep mode: %d\n", ret);
114-
return ret;
115-
}
116-
msleep(120);
117-
118-
ret = mipi_dsi_dcs_set_display_on(dsi);
119-
if (ret < 0) {
120-
dev_err(dev, "Failed to set display on: %d\n", ret);
121-
return ret;
122-
}
123-
msleep(20);
124-
125-
return 0;
47+
mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
48+
49+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx,
50+
MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x20);
51+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx,
52+
MIPI_DCS_SET_DISPLAY_BRIGHTNESS, 0x00,
53+
0x00);
54+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x09);
55+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x01);
56+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00);
57+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x01);
58+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x12, 0x00, 0x00, 0xab,
59+
0x30, 0x80, 0x09, 0x60, 0x04, 0x38, 0x00,
60+
0x28, 0x02, 0x1c, 0x02, 0x1c, 0x02, 0x00,
61+
0x02, 0x0e, 0x00, 0x20, 0x03, 0xdd, 0x00,
62+
0x07, 0x00, 0x0c, 0x02, 0x77, 0x02, 0x8b,
63+
0x18, 0x00, 0x10, 0xf0, 0x07, 0x10, 0x20,
64+
0x00, 0x06, 0x0f, 0x0f, 0x33, 0x0e, 0x1c,
65+
0x2a, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70,
66+
0x77, 0x79, 0x7b, 0x7d, 0x7e, 0x02, 0x02,
67+
0x22, 0x00, 0x2a, 0x40, 0x2a, 0xbe, 0x3a,
68+
0xfc, 0x3a, 0xfa, 0x3a, 0xf8, 0x3b, 0x38,
69+
0x3b, 0x78, 0x3b, 0xb6, 0x4b, 0xb6, 0x4b,
70+
0xf4, 0x4b, 0xf4, 0x6c, 0x34, 0x84, 0x74,
71+
0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
72+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xaa, 0x10);
73+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb1, 0x01, 0x38, 0x00, 0x14,
74+
0x00, 0x1c, 0x00, 0x01, 0x66, 0x00, 0x14,
75+
0x00, 0x14, 0x00, 0x01, 0x66, 0x00, 0x14,
76+
0x05, 0xcc, 0x00);
77+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xaa, 0x13);
78+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xce, 0x09, 0x11, 0x09, 0x11,
79+
0x08, 0xc1, 0x07, 0xfa, 0x05, 0xa4, 0x00,
80+
0x3c, 0x00, 0x34, 0x00, 0x24, 0x00, 0x0c,
81+
0x00, 0x0c, 0x04, 0x00, 0x35);
82+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xaa, 0x14);
83+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb2, 0x03, 0x33);
84+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb4, 0x00, 0x33, 0x00, 0x00,
85+
0x00, 0x3e, 0x00, 0x00, 0x00, 0x3e, 0x00,
86+
0x00);
87+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb5, 0x00, 0x09, 0x09, 0x09,
88+
0x09, 0x09, 0x09, 0x06, 0x01);
89+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb9, 0x00, 0x00, 0x08, 0x09,
90+
0x09, 0x09);
91+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbc, 0x10, 0x00, 0x00, 0x06,
92+
0x11, 0x09, 0x3b, 0x09, 0x47, 0x09, 0x47,
93+
0x00);
94+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbe, 0x10, 0x10, 0x00, 0x08,
95+
0x22, 0x09, 0x19, 0x09, 0x25, 0x09, 0x25,
96+
0x00);
97+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x5a, 0x80);
98+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x14);
99+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfa, 0x08, 0x08, 0x08);
100+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x5a, 0x81);
101+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x05);
102+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf3, 0x0f);
103+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xaa, 0x00);
104+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x5a, 0x82);
105+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf9, 0x00);
106+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x51, 0x83);
107+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x04);
108+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf8, 0x00);
109+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x5a, 0x00);
110+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x01);
111+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf4, 0x9a);
112+
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x5a, 0x00);
113+
114+
mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
115+
mipi_dsi_msleep(&dsi_ctx, 120);
116+
117+
mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
118+
mipi_dsi_msleep(&dsi_ctx, 20);
119+
120+
return dsi_ctx.accum_err;
126121
}
127122

128-
static int visionox_vtdr6130_off(struct visionox_vtdr6130 *ctx)
123+
static void visionox_vtdr6130_off(struct visionox_vtdr6130 *ctx)
129124
{
130125
struct mipi_dsi_device *dsi = ctx->dsi;
131-
struct device *dev = &dsi->dev;
132-
int ret;
126+
struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
133127

134128
dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
135129

136-
ret = mipi_dsi_dcs_set_display_off(dsi);
137-
if (ret < 0) {
138-
dev_err(dev, "Failed to set display off: %d\n", ret);
139-
return ret;
140-
}
141-
msleep(20);
142-
143-
ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
144-
if (ret < 0) {
145-
dev_err(dev, "Failed to enter sleep mode: %d\n", ret);
146-
return ret;
147-
}
148-
msleep(120);
130+
mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
131+
mipi_dsi_msleep(&dsi_ctx, 20);
149132

150-
return 0;
133+
mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
134+
mipi_dsi_msleep(&dsi_ctx, 120);
151135
}
152136

153137
static int visionox_vtdr6130_prepare(struct drm_panel *panel)
154138
{
155139
struct visionox_vtdr6130 *ctx = to_visionox_vtdr6130(panel);
156-
struct device *dev = &ctx->dsi->dev;
157140
int ret;
158141

159142
ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies),
@@ -165,7 +148,6 @@ static int visionox_vtdr6130_prepare(struct drm_panel *panel)
165148

166149
ret = visionox_vtdr6130_on(ctx);
167150
if (ret < 0) {
168-
dev_err(dev, "Failed to initialize panel: %d\n", ret);
169151
gpiod_set_value_cansleep(ctx->reset_gpio, 1);
170152
regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
171153
return ret;
@@ -177,12 +159,8 @@ static int visionox_vtdr6130_prepare(struct drm_panel *panel)
177159
static int visionox_vtdr6130_unprepare(struct drm_panel *panel)
178160
{
179161
struct visionox_vtdr6130 *ctx = to_visionox_vtdr6130(panel);
180-
struct device *dev = &ctx->dsi->dev;
181-
int ret;
182162

183-
ret = visionox_vtdr6130_off(ctx);
184-
if (ret < 0)
185-
dev_err(dev, "Failed to un-initialize panel: %d\n", ret);
163+
visionox_vtdr6130_off(ctx);
186164

187165
gpiod_set_value_cansleep(ctx->reset_gpio, 1);
188166

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