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AngeloGioacchino Del Regnobebarino
AngeloGioacchino Del Regno
authored and
bebarino
committed
clk: mediatek: mux: Stop forcing CLK_SET_RATE_PARENT flag
The clk-mux driver was forcing the CLK_SET_RATE_PARENT flag even for the GATE_CLK_SET_UPD_FLAGS() macro, as in mtk_clk_register_mux() the flag was unconditionally added. In preparation for a change on MSDC clock muxes, stop forcing this flag and, where necessary, update clock drivers to add it so that with this commit we introduce no functional changes for the currently supported SoCs. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Matthias Brugger <[email protected]> Reviewed-by: Markus Schneider-Pargmann <[email protected]> Link: https://lore.kernel.org/r/[email protected] Tested-by: Alexandre Mergnat <[email protected]> Reviewed-by: Alexandre Mergnat <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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9 files changed

+62
-40
lines changed

9 files changed

+62
-40
lines changed

‎drivers/clk/mediatek/clk-mt6765.c

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -367,10 +367,12 @@ static const struct mtk_mux top_muxes[] = {
367367
/* CLK_CFG_0 */
368368
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
369369
CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
370-
0, 2, 7, CLK_CFG_UPDATE, 0, CLK_IS_CRITICAL),
370+
0, 2, 7, CLK_CFG_UPDATE, 0,
371+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
371372
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
372373
CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
373-
8, 2, 15, CLK_CFG_UPDATE, 1, CLK_IS_CRITICAL),
374+
8, 2, 15, CLK_CFG_UPDATE, 1,
375+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
374376
MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
375377
CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23,
376378
CLK_CFG_UPDATE, 2),
@@ -459,7 +461,7 @@ static const struct mtk_mux top_muxes[] = {
459461
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRAP_ULPOSC_SEL, "ulposc_sel",
460462
ulposc_parents, CLK_CFG_7, CLK_CFG_7_SET,
461463
CLK_CFG_7_CLR, 0, 3, 7, CLK_CFG_UPDATE, 28,
462-
CLK_IS_CRITICAL),
464+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
463465
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", camtm_parents,
464466
CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 8, 2, 15,
465467
CLK_CFG_UPDATE, 29),

‎drivers/clk/mediatek/clk-mt6779.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -640,7 +640,7 @@ static const struct mtk_mux top_muxes[] = {
640640
/* CLK_CFG_0 */
641641
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "axi_sel", axi_parents,
642642
0x20, 0x24, 0x28, 0, 2, 7,
643-
0x004, 0, CLK_IS_CRITICAL),
643+
0x004, 0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
644644
MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents,
645645
0x20, 0x24, 0x28, 8, 3, 15, 0x004, 1),
646646
MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP, "scp_sel", scp_parents,
@@ -710,7 +710,7 @@ static const struct mtk_mux top_muxes[] = {
710710
0x90, 0x94, 0x98, 0, 2, 7, 0x004, 28),
711711
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "sspm_sel", sspm_parents,
712712
0x90, 0x94, 0x98, 8, 3, 15,
713-
0x004, 29, CLK_IS_CRITICAL),
713+
0x004, 29, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
714714
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0, "dpi0_sel", dpi0_parents,
715715
0x90, 0x94, 0x98, 16, 3, 23, 0x004, 30),
716716
MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM, "scam_sel", scam_parents,
@@ -727,7 +727,7 @@ static const struct mtk_mux top_muxes[] = {
727727
16, 2, 23, 0x008, 3),
728728
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "spm_sel", spm_parents,
729729
0xa0, 0xa4, 0xa8, 24, 2, 31,
730-
0x008, 4, CLK_IS_CRITICAL),
730+
0x008, 4, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
731731
/* CLK_CFG_9 */
732732
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "i2c_sel", i2c_parents,
733733
0xb0, 0xb4, 0xb8, 0, 2, 7, 0x008, 5),

‎drivers/clk/mediatek/clk-mt8183.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -451,7 +451,8 @@ static const char * const aud_2_parents[] = {
451451
static const struct mtk_mux top_muxes[] = {
452452
/* CLK_CFG_0 */
453453
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel",
454-
axi_parents, 0x40, 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL),
454+
axi_parents, 0x40, 0x44, 0x48, 0, 2, 7, 0x004, 0,
455+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
455456
MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel",
456457
mm_parents, 0x40, 0x44, 0x48, 8, 3, 15, 0x004, 1),
457458
MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel",
@@ -518,7 +519,8 @@ static const struct mtk_mux top_muxes[] = {
518519
MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
519520
ssusb_top_xhci_parents, 0xb0, 0xb4, 0xb8, 16, 2, 23, 0x004, 30),
520521
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_SPM, "spm_sel",
521-
spm_parents, 0xb0, 0xb4, 0xb8, 24, 1, 31, 0x008, 0, CLK_IS_CRITICAL),
522+
spm_parents, 0xb0, 0xb4, 0xb8, 24, 1, 31, 0x008, 0,
523+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
522524
/* CLK_CFG_8 */
523525
MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_I2C, "i2c_sel",
524526
i2c_parents, 0xc0, 0xc4, 0xc8, 0, 2, 7, 0x008, 1),

‎drivers/clk/mediatek/clk-mt8186-topckgen.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -504,10 +504,10 @@ static const struct mtk_mux top_mtk_muxes[] = {
504504
*/
505505
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi", axi_parents,
506506
0x0040, 0x0044, 0x0048, 0, 2, 7, 0x0004, 0,
507-
CLK_IS_CRITICAL),
507+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
508508
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp", scp_parents,
509509
0x0040, 0x0044, 0x0048, 8, 3, 15, 0x0004, 1,
510-
CLK_IS_CRITICAL),
510+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
511511
MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "top_mfg",
512512
mfg_parents, 0x0040, 0x0044, 0x0048, 16, 2, 23, 0x0004, 2),
513513
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
@@ -559,7 +559,7 @@ static const struct mtk_mux top_mtk_muxes[] = {
559559
disp_pwm_parents, 0x0090, 0x0094, 0x0098, 8, 3, 15, 0x0004, 21),
560560
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "top_sspm", sspm_parents,
561561
0x0090, 0x0094, 0x0098, 16, 3, 23, 0x0004, 22,
562-
CLK_IS_CRITICAL),
562+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
563563
MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "top_dxcc",
564564
dxcc_parents, 0x0090, 0x0094, 0x0098, 24, 2, 31, 0x0004, 23),
565565
/*
@@ -570,10 +570,10 @@ static const struct mtk_mux top_mtk_muxes[] = {
570570
usb_parents, 0x00a0, 0x00a4, 0x00a8, 0, 2, 7, 0x0004, 24),
571571
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck", srck_parents,
572572
0x00a0, 0x00a4, 0x00a8, 8, 2, 15, 0x0004, 25,
573-
CLK_IS_CRITICAL),
573+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
574574
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm", spm_parents,
575575
0x00a0, 0x00a4, 0x00a8, 16, 2, 23, 0x0004, 26,
576-
CLK_IS_CRITICAL),
576+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
577577
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
578578
i2c_parents, 0x00a0, 0x00a4, 0x00a8, 24, 2, 31, 0x0004, 27),
579579
/* CLK_CFG_7 */
@@ -627,7 +627,7 @@ static const struct mtk_mux top_mtk_muxes[] = {
627627
*/
628628
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc", dvfsrc_parents,
629629
0x0100, 0x0104, 0x0108, 0, 1, 7, 0x0008, 17,
630-
CLK_IS_CRITICAL),
630+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
631631
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
632632
dsi_occ_parents, 0x0100, 0x0104, 0x0108, 8, 2, 15, 0x0008, 18),
633633
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_MST, "top_spmi_mst",

‎drivers/clk/mediatek/clk-mt8188-topckgen.c

Lines changed: 16 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -954,13 +954,17 @@ static const struct mtk_mux top_mtk_muxes[] = {
954954
* spm_sel and scp_sel are main clocks in always-on co-processor.
955955
*/
956956
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi", axi_parents,
957-
0x020, 0x024, 0x028, 0, 4, 7, 0x04, 0, CLK_IS_CRITICAL),
957+
0x020, 0x024, 0x028, 0, 4, 7, 0x04, 0,
958+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
958959
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm", spm_parents,
959-
0x020, 0x024, 0x028, 8, 4, 15, 0x04, 1, CLK_IS_CRITICAL),
960+
0x020, 0x024, 0x028, 8, 4, 15, 0x04, 1,
961+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
960962
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp", scp_parents,
961-
0x020, 0x024, 0x028, 16, 4, 23, 0x04, 2, CLK_IS_CRITICAL),
963+
0x020, 0x024, 0x028, 16, 4, 23, 0x04, 2,
964+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
962965
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM, "top_bus_aximem", bus_aximem_parents,
963-
0x020, 0x024, 0x028, 24, 4, 31, 0x04, 3, CLK_IS_CRITICAL),
966+
0x020, 0x024, 0x028, 24, 4, 31, 0x04, 3,
967+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
964968
/* CLK_CFG_1 */
965969
MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
966970
vpp_parents, 0x02C, 0x030, 0x034, 0, 4, 7, 0x04, 4),
@@ -1078,7 +1082,8 @@ static const struct mtk_mux top_mtk_muxes[] = {
10781082
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
10791083
pwm_parents, 0x0BC, 0x0C0, 0x0C4, 8, 4, 15, 0x08, 21),
10801084
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MCUPM, "top_mcupm", mcupm_parents,
1081-
0x0BC, 0x0C0, 0x0C4, 16, 4, 23, 0x08, 22, CLK_IS_CRITICAL),
1085+
0x0BC, 0x0C0, 0x0C4, 16, 4, 23, 0x08, 22,
1086+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
10821087
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST, "top_spmi_p_mst",
10831088
spmi_p_mst_parents, 0x0BC, 0x0C0, 0x0C4, 24, 4, 31, 0x08, 23),
10841089
/*
@@ -1088,7 +1093,8 @@ static const struct mtk_mux top_mtk_muxes[] = {
10881093
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst",
10891094
spmi_m_mst_parents, 0x0C8, 0x0CC, 0x0D0, 0, 4, 7, 0x08, 24),
10901095
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc", dvfsrc_parents,
1091-
0x0C8, 0x0CC, 0x0D0, 8, 4, 15, 0x08, 25, CLK_IS_CRITICAL),
1096+
0x0C8, 0x0CC, 0x0D0, 8, 4, 15, 0x08, 25,
1097+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
10921098
MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl",
10931099
tl_parents, 0x0C8, 0x0CC, 0x0D0, 16, 4, 23, 0x08, 26),
10941100
MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde",
@@ -1164,9 +1170,11 @@ static const struct mtk_mux top_mtk_muxes[] = {
11641170
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",
11651171
spinor_parents, 0x0128, 0x012C, 0x0130, 0, 4, 7, 0x0C, 24),
11661172
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC, "top_ulposc", ulposc_parents,
1167-
0x0128, 0x012C, 0x0130, 8, 4, 15, 0x0C, 25, CLK_IS_CRITICAL),
1173+
0x0128, 0x012C, 0x0130, 8, 4, 15, 0x0C, 25,
1174+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
11681175
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck", srck_parents,
1169-
0x0128, 0x012C, 0x0130, 16, 4, 23, 0x0C, 26, CLK_IS_CRITICAL),
1176+
0x0128, 0x012C, 0x0130, 16, 4, 23, 0x0C, 26,
1177+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
11701178
};
11711179

11721180
static const struct mtk_composite top_adj_divs[] = {

‎drivers/clk/mediatek/clk-mt8192.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -549,15 +549,15 @@ static const struct mtk_mux top_mtk_muxes[] = {
549549
/* CLK_CFG_0 */
550550
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel",
551551
axi_parents, 0x010, 0x014, 0x018, 0, 3, 7, 0x004, 0,
552-
CLK_IS_CRITICAL),
552+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
553553
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel",
554554
spm_parents, 0x010, 0x014, 0x018, 8, 2, 15, 0x004, 1,
555-
CLK_IS_CRITICAL),
555+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
556556
MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel",
557557
scp_parents, 0x010, 0x014, 0x018, 16, 3, 23, 0x004, 2),
558558
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM_SEL, "bus_aximem_sel",
559559
bus_aximem_parents, 0x010, 0x014, 0x018, 24, 3, 31, 0x004, 3,
560-
CLK_IS_CRITICAL),
560+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
561561
/* CLK_CFG_1 */
562562
MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_SEL, "disp_sel",
563563
disp_parents, 0x020, 0x024, 0x028, 0, 4, 7, 0x004, 4),

‎drivers/clk/mediatek/clk-mt8195-topckgen.c

Lines changed: 20 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -862,13 +862,17 @@ static const struct mtk_mux top_mtk_muxes[] = {
862862
* top_spm and top_scp are main clocks in always-on co-processor.
863863
*/
864864
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi",
865-
axi_parents, 0x020, 0x024, 0x028, 0, 3, 7, 0x04, 0, CLK_IS_CRITICAL),
865+
axi_parents, 0x020, 0x024, 0x028, 0, 3, 7, 0x04, 0,
866+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
866867
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm",
867-
spm_parents, 0x020, 0x024, 0x028, 8, 2, 15, 0x04, 1, CLK_IS_CRITICAL),
868+
spm_parents, 0x020, 0x024, 0x028, 8, 2, 15, 0x04, 1,
869+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
868870
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp",
869-
scp_parents, 0x020, 0x024, 0x028, 16, 3, 23, 0x04, 2, CLK_IS_CRITICAL),
871+
scp_parents, 0x020, 0x024, 0x028, 16, 3, 23, 0x04, 2,
872+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
870873
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM, "top_bus_aximem",
871-
bus_aximem_parents, 0x020, 0x024, 0x028, 24, 3, 31, 0x04, 3, CLK_IS_CRITICAL),
874+
bus_aximem_parents, 0x020, 0x024, 0x028, 24, 3, 31, 0x04, 3,
875+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
872876
/* CLK_CFG_1 */
873877
MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
874878
vpp_parents, 0x02C, 0x030, 0x034, 0, 4, 7, 0x04, 4),
@@ -951,7 +955,8 @@ static const struct mtk_mux top_mtk_muxes[] = {
951955
MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "top_atb",
952956
atb_parents, 0x08C, 0x090, 0x094, 8, 2, 15, 0x08, 5),
953957
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRMCU, "top_pwrmcu",
954-
pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6, CLK_IS_CRITICAL),
958+
pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6,
959+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
955960
MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp",
956961
dp_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7),
957962
/* CLK_CFG_10 */
@@ -1020,7 +1025,8 @@ static const struct mtk_mux top_mtk_muxes[] = {
10201025
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
10211026
pwm_parents, 0x0E0, 0x0E4, 0x0E8, 16, 1, 23, 0x0C, 2),
10221027
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MCUPM, "top_mcupm",
1023-
mcupm_parents, 0x0E0, 0x0E4, 0x0E8, 24, 2, 31, 0x0C, 3, CLK_IS_CRITICAL),
1028+
mcupm_parents, 0x0E0, 0x0E4, 0x0E8, 24, 2, 31, 0x0C, 3,
1029+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
10241030
/*
10251031
* CLK_CFG_17
10261032
* top_dvfsrc is for internal DVFS usage, should not be handled by Linux.
@@ -1030,7 +1036,8 @@ static const struct mtk_mux top_mtk_muxes[] = {
10301036
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst",
10311037
spmi_parents, 0x0EC, 0x0F0, 0x0F4, 8, 4, 15, 0x0C, 5),
10321038
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc",
1033-
dvfsrc_parents, 0x0EC, 0x0F0, 0x0F4, 16, 2, 23, 0x0C, 6, CLK_IS_CRITICAL),
1039+
dvfsrc_parents, 0x0EC, 0x0F0, 0x0F4, 16, 2, 23, 0x0C, 6,
1040+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
10341041
MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl",
10351042
tl_parents, 0x0EC, 0x0F0, 0x0F4, 24, 2, 31, 0x0C, 7),
10361043
/* CLK_CFG_18 */
@@ -1141,11 +1148,14 @@ static const struct mtk_mux top_mtk_muxes[] = {
11411148
MUX_GATE_CLR_SET_UPD(CLK_TOP_DVIO_DGI_REF, "top_dvio_dgi_ref",
11421149
dvio_dgi_ref_parents, 0x017C, 0x0180, 0x0184, 0, 3, 7, 0x010, 20),
11431150
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC, "top_ulposc",
1144-
ulposc_parents, 0x017C, 0x0180, 0x0184, 8, 2, 15, 0x010, 21, CLK_IS_CRITICAL),
1151+
ulposc_parents, 0x017C, 0x0180, 0x0184, 8, 2, 15, 0x010, 21,
1152+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
11451153
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC_CORE, "top_ulposc_core",
1146-
ulposc_core_parents, 0x017C, 0x0180, 0x0184, 16, 2, 23, 0x010, 22, CLK_IS_CRITICAL),
1154+
ulposc_core_parents, 0x017C, 0x0180, 0x0184, 16, 2, 23, 0x010, 22,
1155+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
11471156
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck",
1148-
srck_parents, 0x017C, 0x0180, 0x0184, 24, 1, 31, 0x010, 23, CLK_IS_CRITICAL),
1157+
srck_parents, 0x017C, 0x0180, 0x0184, 24, 1, 31, 0x010, 23,
1158+
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
11491159
/*
11501160
* the clocks in CLK_CFG_30 ~ 37 are backup clock source, no need to handled
11511161
* by Linux.

‎drivers/clk/mediatek/clk-mt8365.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -410,7 +410,7 @@ static const struct mtk_mux top_muxes[] = {
410410
/* CLK_CFG_0 */
411411
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
412412
0x040, 0x044, 0x048, 0, 2, 7, CLK_CFG_UPDATE,
413-
0, CLK_IS_CRITICAL),
413+
0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
414414
MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040,
415415
0x044, 0x048, 8, 2, 15, CLK_CFG_UPDATE, 1),
416416
MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 0x044,
@@ -475,16 +475,16 @@ static const struct mtk_mux top_muxes[] = {
475475
/* CLK_CFG_6 */
476476
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents,
477477
0x0a0, 0x0a4, 0x0a8, 0, 2, 7, CLK_CFG_UPDATE,
478-
24, CLK_IS_CRITICAL),
478+
24, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
479479
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_SYS_SEL, "ssusb_sys_sel",
480480
ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 8, 2, 15,
481481
CLK_CFG_UPDATE, 25),
482482
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel",
483483
ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 16, 2, 23,
484484
CLK_CFG_UPDATE, 26),
485485
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", spm_parents,
486-
0x0a0, 0x0a4, 0x0a8, 24, 1, 31,
487-
CLK_CFG_UPDATE, 27, CLK_IS_CRITICAL),
486+
0x0a0, 0x0a4, 0x0a8, 24, 1, 31, CLK_CFG_UPDATE,
487+
27, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
488488
/* CLK_CFG_7 */
489489
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x0b0,
490490
0x0b4, 0x0b8, 0, 3, 7, CLK_CFG_UPDATE, 28),

‎drivers/clk/mediatek/clk-mux.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -168,7 +168,7 @@ static struct clk_hw *mtk_clk_register_mux(struct device *dev,
168168
return ERR_PTR(-ENOMEM);
169169

170170
init.name = mux->name;
171-
init.flags = mux->flags | CLK_SET_RATE_PARENT;
171+
init.flags = mux->flags;
172172
init.parent_names = mux->parent_names;
173173
init.num_parents = mux->num_parents;
174174
init.ops = mux->ops;

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