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126 | 126 | #define E_ECAM_CR_ENABLE BIT(0)
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127 | 127 | #define E_ECAM_SIZE_LOC GENMASK(20, 16)
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128 | 128 | #define E_ECAM_SIZE_SHIFT 16
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129 |
| -#define NWL_ECAM_VALUE_DEFAULT 12 |
| 129 | +#define NWL_ECAM_MAX_SIZE 12 |
130 | 130 |
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131 | 131 | #define CFG_DMA_REG_BAR GENMASK(2, 0)
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132 | 132 | #define CFG_PCIE_CACHE GENMASK(7, 0)
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@@ -165,7 +165,6 @@ struct nwl_pcie {
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165 | 165 | u32 ecam_size;
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166 | 166 | int irq_intx;
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167 | 167 | int irq_misc;
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168 |
| - u32 ecam_value; |
169 | 168 | struct nwl_msi msi;
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170 | 169 | struct irq_domain *legacy_irq_domain;
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171 | 170 | struct clk *clk;
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@@ -674,7 +673,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
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674 | 673 | E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
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675 | 674 |
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676 | 675 | nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
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677 |
| - (pcie->ecam_value << E_ECAM_SIZE_SHIFT), |
| 676 | + (NWL_ECAM_MAX_SIZE << E_ECAM_SIZE_SHIFT), |
678 | 677 | E_ECAM_CONTROL);
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679 | 678 |
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680 | 679 | nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
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@@ -782,7 +781,6 @@ static int nwl_pcie_probe(struct platform_device *pdev)
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782 | 781 | pcie = pci_host_bridge_priv(bridge);
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783 | 782 |
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784 | 783 | pcie->dev = dev;
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785 |
| - pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; |
786 | 784 |
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787 | 785 | err = nwl_pcie_parse_dt(pcie, pdev);
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788 | 786 | if (err) {
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