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KVM: arm64: Spin off helper for programming CPTR traps
A subsequent change to KVM will add preliminary support for merging a guest hypervisor's CPTR traps with that of KVM. Prepare by spinning off a new helper for managing CPTR traps. Avoid reading CPACR_EL1 for the baseline trap config, and start off with the most restrictive set of traps that is subsequently relaxed. Reviewed-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Oliver Upton <[email protected]>
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arch/arm64/kvm/hyp/vhe/switch.c

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -65,6 +65,29 @@ static u64 __compute_hcr(struct kvm_vcpu *vcpu)
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return hcr | (__vcpu_sys_reg(vcpu, HCR_EL2) & ~NV_HCR_GUEST_EXCLUDE);
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}
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68+
static void __activate_cptr_traps(struct kvm_vcpu *vcpu)
69+
{
70+
/*
71+
* With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
72+
* CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
73+
* except for some missing controls, such as TAM.
74+
* In this case, CPTR_EL2.TAM has the same position with or without
75+
* VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
76+
* shift value for trapping the AMU accesses.
77+
*/
78+
u64 val = CPACR_ELx_TTA | CPTR_EL2_TAM;
79+
80+
if (guest_owns_fp_regs()) {
81+
val |= CPACR_ELx_FPEN;
82+
if (vcpu_has_sve(vcpu))
83+
val |= CPACR_ELx_ZEN;
84+
} else {
85+
__activate_traps_fpsimd32(vcpu);
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}
87+
88+
write_sysreg(val, cpacr_el1);
89+
}
90+
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static void __activate_traps(struct kvm_vcpu *vcpu)
6992
{
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u64 val;
@@ -91,30 +114,7 @@ static void __activate_traps(struct kvm_vcpu *vcpu)
91114
}
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}
93116

94-
val = read_sysreg(cpacr_el1);
95-
val |= CPACR_ELx_TTA;
96-
val &= ~(CPACR_ELx_ZEN | CPACR_ELx_SMEN);
97-
98-
/*
99-
* With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
100-
* CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
101-
* except for some missing controls, such as TAM.
102-
* In this case, CPTR_EL2.TAM has the same position with or without
103-
* VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
104-
* shift value for trapping the AMU accesses.
105-
*/
106-
107-
val |= CPTR_EL2_TAM;
108-
109-
if (guest_owns_fp_regs()) {
110-
if (vcpu_has_sve(vcpu))
111-
val |= CPACR_ELx_ZEN;
112-
} else {
113-
val &= ~CPACR_ELx_FPEN;
114-
__activate_traps_fpsimd32(vcpu);
115-
}
116-
117-
write_sysreg(val, cpacr_el1);
117+
__activate_cptr_traps(vcpu);
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119119
write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1);
120120
}

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