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ARC: boot log: eliminate struct cpuinfo_arc #2: cache
Signed-off-by: Vineet Gupta <[email protected]>
1 parent 72d861f commit 17a5ed5

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4 files changed

+97
-115
lines changed

4 files changed

+97
-115
lines changed

‎arch/arc/include/asm/arcregs.h

Lines changed: 32 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -206,6 +206,38 @@ struct bcr_mmu_4 {
206206
#endif
207207
};
208208

209+
struct bcr_cache {
210+
#ifdef CONFIG_CPU_BIG_ENDIAN
211+
unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
212+
#else
213+
unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
214+
#endif
215+
};
216+
217+
struct bcr_slc_cfg {
218+
#ifdef CONFIG_CPU_BIG_ENDIAN
219+
unsigned int pad:24, way:2, lsz:2, sz:4;
220+
#else
221+
unsigned int sz:4, lsz:2, way:2, pad:24;
222+
#endif
223+
};
224+
225+
struct bcr_clust_cfg {
226+
#ifdef CONFIG_CPU_BIG_ENDIAN
227+
unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
228+
#else
229+
unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
230+
#endif
231+
};
232+
233+
struct bcr_volatile {
234+
#ifdef CONFIG_CPU_BIG_ENDIAN
235+
unsigned int start:4, limit:4, pad:22, order:1, disable:1;
236+
#else
237+
unsigned int disable:1, order:1, pad:22, limit:4, start:4;
238+
#endif
239+
};
240+
209241
struct bcr_mpy {
210242
#ifdef CONFIG_CPU_BIG_ENDIAN
211243
unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
@@ -328,10 +360,6 @@ struct bcr_generic {
328360
* Generic structures to hold build configuration used at runtime
329361
*/
330362

331-
struct cpuinfo_arc_cache {
332-
unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4;
333-
};
334-
335363
struct cpuinfo_arc_bpu {
336364
unsigned int ver, full, num_cache, num_pred, ret_stk;
337365
};
@@ -341,7 +369,6 @@ struct cpuinfo_arc_ccm {
341369
};
342370

343371
struct cpuinfo_arc {
344-
struct cpuinfo_arc_cache icache, dcache, slc;
345372
struct cpuinfo_arc_bpu bpu;
346373
struct bcr_identity core;
347374
struct bcr_isa_arcv2 isa;

‎arch/arc/include/asm/setup.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,6 @@ extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
3939

4040
extern void arc_cache_init(void);
4141
extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
42-
extern void read_decode_cache_bcr(void);
4342

4443
extern void __init handle_uboot_args(void);
4544

‎arch/arc/kernel/setup.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -186,8 +186,6 @@ static void read_arc_build_cfg_regs(void)
186186
/* Read CCM BCRs for boot reporting even if not enabled in Kconfig */
187187
read_decode_ccm_bcr(cpu);
188188

189-
read_decode_cache_bcr();
190-
191189
if (is_isa_arcompact()) {
192190
struct bcr_fp_arcompact sp, dp;
193191
struct bcr_bpu_arcompact bpu;
@@ -463,6 +461,7 @@ void setup_processor(void)
463461

464462
pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
465463
pr_info("%s", arc_mmu_mumbojumbo(cpu_id, str, sizeof(str)));
464+
pr_info("%s", arc_cache_mumbojumbo(cpu_id, str, sizeof(str)));
466465

467466
arc_mmu_init();
468467
arc_cache_init();

‎arch/arc/mm/cache.c

Lines changed: 64 additions & 107 deletions
Original file line numberDiff line numberDiff line change
@@ -28,85 +28,35 @@ int slc_enable = 1, ioc_enable = 1;
2828
unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */
2929
unsigned long perip_end = 0xFFFFFFFF; /* legacy value */
3030

31+
static struct cpuinfo_arc_cache {
32+
unsigned int sz_k, line_len, colors;
33+
} ic_info, dc_info, slc_info;
34+
3135
void (*_cache_line_loop_ic_fn)(phys_addr_t paddr, unsigned long vaddr,
3236
unsigned long sz, const int op, const int full_page);
3337

3438
void (*__dma_cache_wback_inv)(phys_addr_t start, unsigned long sz);
3539
void (*__dma_cache_inv)(phys_addr_t start, unsigned long sz);
3640
void (*__dma_cache_wback)(phys_addr_t start, unsigned long sz);
3741

38-
char *arc_cache_mumbojumbo(int c, char *buf, int len)
42+
static char *read_decode_cache_bcr_arcv2(int c, char *buf, int len)
3943
{
40-
int n = 0;
41-
struct cpuinfo_arc_cache *p;
42-
43-
#define PR_CACHE(p, cfg, str) \
44-
if (!(p)->line_len) \
45-
n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \
46-
else \
47-
n += scnprintf(buf + n, len - n, \
48-
str"\t\t: %uK, %dway/set, %uB Line, %s%s%s\n", \
49-
(p)->sz_k, (p)->assoc, (p)->line_len, \
50-
(p)->vipt ? "VIPT" : "PIPT", \
51-
(p)->alias ? " aliasing" : "", \
52-
IS_USED_CFG(cfg));
53-
54-
PR_CACHE(&cpuinfo_arc700[c].icache, CONFIG_ARC_HAS_ICACHE, "I-Cache");
55-
PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache");
56-
57-
p = &cpuinfo_arc700[c].slc;
58-
if (p->line_len)
59-
n += scnprintf(buf + n, len - n,
60-
"SLC\t\t: %uK, %uB Line%s\n",
61-
p->sz_k, p->line_len, IS_USED_RUN(slc_enable));
62-
63-
n += scnprintf(buf + n, len - n, "Peripherals\t: %#lx%s%s\n",
64-
perip_base,
65-
IS_AVAIL3(ioc_exists, ioc_enable, ", IO-Coherency (per-device) "));
66-
67-
return buf;
68-
}
69-
70-
/*
71-
* Read the Cache Build Confuration Registers, Decode them and save into
72-
* the cpuinfo structure for later use.
73-
* No Validation done here, simply read/convert the BCRs
74-
*/
75-
static void read_decode_cache_bcr_arcv2(int cpu)
76-
{
77-
struct cpuinfo_arc_cache *p_slc = &cpuinfo_arc700[cpu].slc;
44+
struct cpuinfo_arc_cache *p_slc = &slc_info;
45+
struct bcr_identity ident;
7846
struct bcr_generic sbcr;
79-
80-
struct bcr_slc_cfg {
81-
#ifdef CONFIG_CPU_BIG_ENDIAN
82-
unsigned int pad:24, way:2, lsz:2, sz:4;
83-
#else
84-
unsigned int sz:4, lsz:2, way:2, pad:24;
85-
#endif
86-
} slc_cfg;
87-
88-
struct bcr_clust_cfg {
89-
#ifdef CONFIG_CPU_BIG_ENDIAN
90-
unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
91-
#else
92-
unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
93-
#endif
94-
} cbcr;
95-
96-
struct bcr_volatile {
97-
#ifdef CONFIG_CPU_BIG_ENDIAN
98-
unsigned int start:4, limit:4, pad:22, order:1, disable:1;
99-
#else
100-
unsigned int disable:1, order:1, pad:22, limit:4, start:4;
101-
#endif
102-
} vol;
103-
47+
struct bcr_clust_cfg cbcr;
48+
struct bcr_volatile vol;
49+
int n = 0;
10450

10551
READ_BCR(ARC_REG_SLC_BCR, sbcr);
10652
if (sbcr.ver) {
53+
struct bcr_slc_cfg slc_cfg;
10754
READ_BCR(ARC_REG_SLC_CFG, slc_cfg);
10855
p_slc->sz_k = 128 << slc_cfg.sz;
10956
l2_line_sz = p_slc->line_len = (slc_cfg.lsz == 0) ? 128 : 64;
57+
n += scnprintf(buf + n, len - n,
58+
"SLC\t\t: %uK, %uB Line%s\n",
59+
p_slc->sz_k, p_slc->line_len, IS_USED_RUN(slc_enable));
11060
}
11161

11262
READ_BCR(ARC_REG_CLUSTER_BCR, cbcr);
@@ -129,70 +79,83 @@ static void read_decode_cache_bcr_arcv2(int cpu)
12979
ioc_enable = 0;
13080
}
13181

82+
READ_BCR(AUX_IDENTITY, ident);
83+
13284
/* HS 2.0 didn't have AUX_VOL */
133-
if (cpuinfo_arc700[cpu].core.family > 0x51) {
85+
if (ident.family > 0x51) {
13486
READ_BCR(AUX_VOL, vol);
13587
perip_base = vol.start << 28;
13688
/* HS 3.0 has limit and strict-ordering fields */
137-
if (cpuinfo_arc700[cpu].core.family > 0x52)
89+
if (ident.family > 0x52)
13890
perip_end = (vol.limit << 28) - 1;
13991
}
92+
93+
n += scnprintf(buf + n, len - n, "Peripherals\t: %#lx%s%s\n",
94+
perip_base,
95+
IS_AVAIL3(ioc_exists, ioc_enable, ", IO-Coherency (per-device) "));
96+
97+
return buf;
14098
}
14199

142-
void read_decode_cache_bcr(void)
100+
char *arc_cache_mumbojumbo(int c, char *buf, int len)
143101
{
144-
struct cpuinfo_arc_cache *p_ic, *p_dc;
145-
unsigned int cpu = smp_processor_id();
146-
struct bcr_cache {
147-
#ifdef CONFIG_CPU_BIG_ENDIAN
148-
unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
149-
#else
150-
unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
151-
#endif
152-
} ibcr, dbcr;
102+
struct cpuinfo_arc_cache *p_ic = &ic_info, *p_dc = &dc_info;
103+
struct bcr_cache ibcr, dbcr;
104+
int vipt, assoc;
105+
int n = 0;
153106

154-
p_ic = &cpuinfo_arc700[cpu].icache;
155107
READ_BCR(ARC_REG_IC_BCR, ibcr);
156-
157108
if (!ibcr.ver)
158109
goto dc_chk;
159110

160-
if (ibcr.ver <= 3) {
111+
if (is_isa_arcompact() && (ibcr.ver <= 3)) {
161112
BUG_ON(ibcr.config != 3);
162-
p_ic->assoc = 2; /* Fixed to 2w set assoc */
163-
} else if (ibcr.ver >= 4) {
164-
p_ic->assoc = 1 << ibcr.config; /* 1,2,4,8 */
113+
assoc = 2; /* Fixed to 2w set assoc */
114+
} else if (is_isa_arcv2() && (ibcr.ver >= 4)) {
115+
assoc = 1 << ibcr.config; /* 1,2,4,8 */
165116
}
166117

167118
p_ic->line_len = 8 << ibcr.line_len;
168119
p_ic->sz_k = 1 << (ibcr.sz - 1);
169-
p_ic->vipt = 1;
170-
p_ic->alias = p_ic->sz_k/p_ic->assoc/TO_KB(PAGE_SIZE) > 1;
120+
p_ic->colors = p_ic->sz_k/assoc/TO_KB(PAGE_SIZE);
121+
122+
n += scnprintf(buf + n, len - n,
123+
"I-Cache\t\t: %uK, %dway/set, %uB Line, VIPT%s%s\n",
124+
p_ic->sz_k, assoc, p_ic->line_len,
125+
p_ic->colors > 1 ? " aliasing" : "",
126+
IS_USED_CFG(CONFIG_ARC_HAS_ICACHE));
171127

172128
dc_chk:
173-
p_dc = &cpuinfo_arc700[cpu].dcache;
174129
READ_BCR(ARC_REG_DC_BCR, dbcr);
175-
176130
if (!dbcr.ver)
177131
goto slc_chk;
178132

179-
if (dbcr.ver <= 3) {
133+
if (is_isa_arcompact() && (dbcr.ver <= 3)) {
180134
BUG_ON(dbcr.config != 2);
181-
p_dc->assoc = 4; /* Fixed to 4w set assoc */
182-
p_dc->vipt = 1;
183-
p_dc->alias = p_dc->sz_k/p_dc->assoc/TO_KB(PAGE_SIZE) > 1;
184-
} else if (dbcr.ver >= 4) {
185-
p_dc->assoc = 1 << dbcr.config; /* 1,2,4,8 */
186-
p_dc->vipt = 0;
187-
p_dc->alias = 0; /* PIPT so can't VIPT alias */
135+
vipt = 1;
136+
assoc = 4; /* Fixed to 4w set assoc */
137+
p_dc->colors = p_dc->sz_k/assoc/TO_KB(PAGE_SIZE);
138+
} else if (is_isa_arcv2() && (dbcr.ver >= 4)) {
139+
vipt = 0;
140+
assoc = 1 << dbcr.config; /* 1,2,4,8 */
141+
p_dc->colors = 1; /* PIPT so can't VIPT alias */
188142
}
189143

190144
p_dc->line_len = 16 << dbcr.line_len;
191145
p_dc->sz_k = 1 << (dbcr.sz - 1);
192146

147+
n += scnprintf(buf + n, len - n,
148+
"D-Cache\t\t: %uK, %dway/set, %uB Line, %s%s%s\n",
149+
p_dc->sz_k, assoc, p_dc->line_len,
150+
vipt ? "VIPT" : "PIPT",
151+
p_dc->colors > 1 ? " aliasing" : "",
152+
IS_USED_CFG(CONFIG_ARC_HAS_DCACHE));
153+
193154
slc_chk:
194155
if (is_isa_arcv2())
195-
read_decode_cache_bcr_arcv2(cpu);
156+
read_decode_cache_bcr_arcv2(c, buf + n, len - n);
157+
158+
return buf;
196159
}
197160

198161
/*
@@ -1133,10 +1096,8 @@ static noinline void __init arc_ioc_setup(void)
11331096
*/
11341097
static noinline void __init arc_cache_init_master(void)
11351098
{
1136-
unsigned int __maybe_unused cpu = smp_processor_id();
1137-
11381099
if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) {
1139-
struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
1100+
struct cpuinfo_arc_cache *ic = &ic_info;
11401101

11411102
if (!ic->line_len)
11421103
panic("cache support enabled but non-existent cache\n");
@@ -1149,14 +1110,14 @@ static noinline void __init arc_cache_init_master(void)
11491110
* In MMU v4 (HS38x) the aliasing icache config uses IVIL/PTAG
11501111
* pair to provide vaddr/paddr respectively, just as in MMU v3
11511112
*/
1152-
if (is_isa_arcv2() && ic->alias)
1113+
if (is_isa_arcv2() && ic->colors > 1)
11531114
_cache_line_loop_ic_fn = __cache_line_loop_v3;
11541115
else
11551116
_cache_line_loop_ic_fn = __cache_line_loop;
11561117
}
11571118

11581119
if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) {
1159-
struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
1120+
struct cpuinfo_arc_cache *dc = &dc_info;
11601121

11611122
if (!dc->line_len)
11621123
panic("cache support enabled but non-existent cache\n");
@@ -1168,14 +1129,13 @@ static noinline void __init arc_cache_init_master(void)
11681129
/* check for D-Cache aliasing on ARCompact: ARCv2 has PIPT */
11691130
if (is_isa_arcompact()) {
11701131
int handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
1171-
int num_colors = dc->sz_k/dc->assoc/TO_KB(PAGE_SIZE);
11721132

1173-
if (dc->alias) {
1133+
if (dc->colors > 1) {
11741134
if (!handled)
11751135
panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
1176-
if (CACHE_COLORS_NUM != num_colors)
1136+
if (CACHE_COLORS_NUM != dc->colors)
11771137
panic("CACHE_COLORS_NUM not optimized for config\n");
1178-
} else if (!dc->alias && handled) {
1138+
} else if (handled && dc->colors == 1) {
11791139
panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
11801140
}
11811141
}
@@ -1218,9 +1178,6 @@ static noinline void __init arc_cache_init_master(void)
12181178
void __ref arc_cache_init(void)
12191179
{
12201180
unsigned int __maybe_unused cpu = smp_processor_id();
1221-
char str[256];
1222-
1223-
pr_info("%s", arc_cache_mumbojumbo(0, str, sizeof(str)));
12241181

12251182
if (!cpu)
12261183
arc_cache_init_master();

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