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1003 | 1003 | <0x00090000 0x00090000 0x002000>, /* ap 55 */
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1004 | 1004 | <0x00092000 0x00092000 0x001000>, /* ap 56 */
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1005 | 1005 | <0x000a4000 0x000a4000 0x001000>, /* ap 57 */
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| 1006 | + <0x000a5000 0x000a5000 0x001000>, |
1006 | 1007 | <0x000a6000 0x000a6000 0x001000>, /* ap 58 */
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1007 | 1008 | <0x000a8000 0x000a8000 0x004000>, /* ap 59 */
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1008 | 1009 | <0x000ac000 0x000ac000 0x001000>, /* ap 60 */
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1908 | 1909 | <0x00001000 0x000a5000 0x00001000>;
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1909 | 1910 | };
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1910 | 1911 |
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| 1912 | + des_target: target-module@a5000 { /* 0x480a5000 */ |
| 1913 | + compatible = "ti,sysc-omap2", "ti,sysc"; |
| 1914 | + reg = <0xa5030 0x4>, |
| 1915 | + <0xa5034 0x4>, |
| 1916 | + <0xa5038 0x4>; |
| 1917 | + reg-names = "rev", "sysc", "syss"; |
| 1918 | + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | |
| 1919 | + SYSC_OMAP2_AUTOIDLE)>; |
| 1920 | + ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| 1921 | + <SYSC_IDLE_NO>, |
| 1922 | + <SYSC_IDLE_SMART>, |
| 1923 | + <SYSC_IDLE_SMART_WKUP>; |
| 1924 | + ti,syss-mask = <1>; |
| 1925 | + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ |
| 1926 | + clocks = <&l4sec_clkctrl OMAP5_DES3DES_CLKCTRL 0>; |
| 1927 | + clock-names = "fck"; |
| 1928 | + #address-cells = <1>; |
| 1929 | + #size-cells = <1>; |
| 1930 | + ranges = <0 0xa5000 0x00001000>; |
| 1931 | + status = "disabled"; |
| 1932 | + |
| 1933 | + des: des@0 { |
| 1934 | + compatible = "ti,omap4-des"; |
| 1935 | + reg = <0 0xa0>; |
| 1936 | + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| 1937 | + dmas = <&sdma 117>, <&sdma 116>; |
| 1938 | + dma-names = "tx", "rx"; |
| 1939 | + }; |
| 1940 | + }; |
| 1941 | + |
1911 | 1942 | target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */
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1912 | 1943 | compatible = "ti,sysc";
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1913 | 1944 | status = "disabled";
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