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Merge tag 'renesas-pinctrl-for-v6.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v6.3 - Add pin groups for Video-In channels 4 and 5 on R-Car H3 ES1.x, - Miscellaneous fixes and improvements.
2 parents 9da134e + 698485c commit 19a2c39

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‎drivers/pinctrl/renesas/pfc-r8a77950.c

Lines changed: 244 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3820,6 +3820,186 @@ static const unsigned int usb31_mux[] = {
38203820
USB31_PWEN_MARK, USB31_OVC_MARK,
38213821
};
38223822

3823+
/* - VIN4 ------------------------------------------------------------------- */
3824+
static const unsigned int vin4_data18_a_pins[] = {
3825+
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3826+
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3827+
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3828+
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3829+
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3830+
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3831+
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3832+
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3833+
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3834+
};
3835+
static const unsigned int vin4_data18_a_mux[] = {
3836+
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3837+
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3838+
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3839+
VI4_DATA10_MARK, VI4_DATA11_MARK,
3840+
VI4_DATA12_MARK, VI4_DATA13_MARK,
3841+
VI4_DATA14_MARK, VI4_DATA15_MARK,
3842+
VI4_DATA18_MARK, VI4_DATA19_MARK,
3843+
VI4_DATA20_MARK, VI4_DATA21_MARK,
3844+
VI4_DATA22_MARK, VI4_DATA23_MARK,
3845+
};
3846+
static const unsigned int vin4_data18_b_pins[] = {
3847+
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3848+
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3849+
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3850+
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3851+
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3852+
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3853+
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3854+
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3855+
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3856+
};
3857+
static const unsigned int vin4_data18_b_mux[] = {
3858+
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3859+
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3860+
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3861+
VI4_DATA10_MARK, VI4_DATA11_MARK,
3862+
VI4_DATA12_MARK, VI4_DATA13_MARK,
3863+
VI4_DATA14_MARK, VI4_DATA15_MARK,
3864+
VI4_DATA18_MARK, VI4_DATA19_MARK,
3865+
VI4_DATA20_MARK, VI4_DATA21_MARK,
3866+
VI4_DATA22_MARK, VI4_DATA23_MARK,
3867+
};
3868+
static const unsigned int vin4_data_a_pins[] = {
3869+
RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3870+
RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3871+
RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3872+
RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3873+
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3874+
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3875+
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3876+
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3877+
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3878+
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3879+
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3880+
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3881+
};
3882+
static const unsigned int vin4_data_a_mux[] = {
3883+
VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3884+
VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3885+
VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3886+
VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3887+
VI4_DATA8_MARK, VI4_DATA9_MARK,
3888+
VI4_DATA10_MARK, VI4_DATA11_MARK,
3889+
VI4_DATA12_MARK, VI4_DATA13_MARK,
3890+
VI4_DATA14_MARK, VI4_DATA15_MARK,
3891+
VI4_DATA16_MARK, VI4_DATA17_MARK,
3892+
VI4_DATA18_MARK, VI4_DATA19_MARK,
3893+
VI4_DATA20_MARK, VI4_DATA21_MARK,
3894+
VI4_DATA22_MARK, VI4_DATA23_MARK,
3895+
};
3896+
static const unsigned int vin4_data_b_pins[] = {
3897+
RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3898+
RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3899+
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3900+
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3901+
RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3902+
RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3903+
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3904+
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3905+
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3906+
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3907+
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3908+
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3909+
};
3910+
static const unsigned int vin4_data_b_mux[] = {
3911+
VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
3912+
VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3913+
VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3914+
VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3915+
VI4_DATA8_MARK, VI4_DATA9_MARK,
3916+
VI4_DATA10_MARK, VI4_DATA11_MARK,
3917+
VI4_DATA12_MARK, VI4_DATA13_MARK,
3918+
VI4_DATA14_MARK, VI4_DATA15_MARK,
3919+
VI4_DATA16_MARK, VI4_DATA17_MARK,
3920+
VI4_DATA18_MARK, VI4_DATA19_MARK,
3921+
VI4_DATA20_MARK, VI4_DATA21_MARK,
3922+
VI4_DATA22_MARK, VI4_DATA23_MARK,
3923+
};
3924+
static const unsigned int vin4_sync_pins[] = {
3925+
/* HSYNC#, VSYNC# */
3926+
RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
3927+
};
3928+
static const unsigned int vin4_sync_mux[] = {
3929+
VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
3930+
};
3931+
static const unsigned int vin4_field_pins[] = {
3932+
/* FIELD */
3933+
RCAR_GP_PIN(1, 16),
3934+
};
3935+
static const unsigned int vin4_field_mux[] = {
3936+
VI4_FIELD_MARK,
3937+
};
3938+
static const unsigned int vin4_clkenb_pins[] = {
3939+
/* CLKENB */
3940+
RCAR_GP_PIN(1, 19),
3941+
};
3942+
static const unsigned int vin4_clkenb_mux[] = {
3943+
VI4_CLKENB_MARK,
3944+
};
3945+
static const unsigned int vin4_clk_pins[] = {
3946+
/* CLK */
3947+
RCAR_GP_PIN(1, 27),
3948+
};
3949+
static const unsigned int vin4_clk_mux[] = {
3950+
VI4_CLK_MARK,
3951+
};
3952+
3953+
/* - VIN5 ------------------------------------------------------------------- */
3954+
static const unsigned int vin5_data_pins[] = {
3955+
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3956+
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3957+
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3958+
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3959+
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3960+
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3961+
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3962+
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3963+
};
3964+
static const unsigned int vin5_data_mux[] = {
3965+
VI5_DATA0_MARK, VI5_DATA1_MARK,
3966+
VI5_DATA2_MARK, VI5_DATA3_MARK,
3967+
VI5_DATA4_MARK, VI5_DATA5_MARK,
3968+
VI5_DATA6_MARK, VI5_DATA7_MARK,
3969+
VI5_DATA8_MARK, VI5_DATA9_MARK,
3970+
VI5_DATA10_MARK, VI5_DATA11_MARK,
3971+
VI5_DATA12_MARK, VI5_DATA13_MARK,
3972+
VI5_DATA14_MARK, VI5_DATA15_MARK,
3973+
};
3974+
static const unsigned int vin5_sync_pins[] = {
3975+
/* HSYNC#, VSYNC# */
3976+
RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3977+
};
3978+
static const unsigned int vin5_sync_mux[] = {
3979+
VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
3980+
};
3981+
static const unsigned int vin5_field_pins[] = {
3982+
RCAR_GP_PIN(1, 11),
3983+
};
3984+
static const unsigned int vin5_field_mux[] = {
3985+
/* FIELD */
3986+
VI5_FIELD_MARK,
3987+
};
3988+
static const unsigned int vin5_clkenb_pins[] = {
3989+
RCAR_GP_PIN(1, 20),
3990+
};
3991+
static const unsigned int vin5_clkenb_mux[] = {
3992+
/* CLKENB */
3993+
VI5_CLKENB_MARK,
3994+
};
3995+
static const unsigned int vin5_clk_pins[] = {
3996+
RCAR_GP_PIN(1, 21),
3997+
};
3998+
static const unsigned int vin5_clk_mux[] = {
3999+
/* CLK */
4000+
VI5_CLK_MARK,
4001+
};
4002+
38234003
static const struct sh_pfc_pin_group pinmux_groups[] = {
38244004
SH_PFC_PIN_GROUP(audio_clk_a_a),
38254005
SH_PFC_PIN_GROUP(audio_clk_a_b),
@@ -4141,6 +4321,34 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
41414321
SH_PFC_PIN_GROUP(usb2),
41424322
SH_PFC_PIN_GROUP(usb30),
41434323
SH_PFC_PIN_GROUP(usb31),
4324+
BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
4325+
BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
4326+
BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
4327+
BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
4328+
SH_PFC_PIN_GROUP(vin4_data18_a),
4329+
BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
4330+
BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
4331+
BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
4332+
BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
4333+
BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
4334+
BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
4335+
SH_PFC_PIN_GROUP(vin4_data18_b),
4336+
BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
4337+
BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
4338+
SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
4339+
SH_PFC_PIN_GROUP(vin4_sync),
4340+
SH_PFC_PIN_GROUP(vin4_field),
4341+
SH_PFC_PIN_GROUP(vin4_clkenb),
4342+
SH_PFC_PIN_GROUP(vin4_clk),
4343+
BUS_DATA_PIN_GROUP(vin5_data, 8),
4344+
BUS_DATA_PIN_GROUP(vin5_data, 10),
4345+
BUS_DATA_PIN_GROUP(vin5_data, 12),
4346+
BUS_DATA_PIN_GROUP(vin5_data, 16),
4347+
SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
4348+
SH_PFC_PIN_GROUP(vin5_sync),
4349+
SH_PFC_PIN_GROUP(vin5_field),
4350+
SH_PFC_PIN_GROUP(vin5_clkenb),
4351+
SH_PFC_PIN_GROUP(vin5_clk),
41444352
};
41454353

41464354
static const char * const audio_clk_groups[] = {
@@ -4637,6 +4845,40 @@ static const char * const usb31_groups[] = {
46374845
"usb31",
46384846
};
46394847

4848+
static const char * const vin4_groups[] = {
4849+
"vin4_data8_a",
4850+
"vin4_data10_a",
4851+
"vin4_data12_a",
4852+
"vin4_data16_a",
4853+
"vin4_data18_a",
4854+
"vin4_data20_a",
4855+
"vin4_data24_a",
4856+
"vin4_data8_b",
4857+
"vin4_data10_b",
4858+
"vin4_data12_b",
4859+
"vin4_data16_b",
4860+
"vin4_data18_b",
4861+
"vin4_data20_b",
4862+
"vin4_data24_b",
4863+
"vin4_g8",
4864+
"vin4_sync",
4865+
"vin4_field",
4866+
"vin4_clkenb",
4867+
"vin4_clk",
4868+
};
4869+
4870+
static const char * const vin5_groups[] = {
4871+
"vin5_data8",
4872+
"vin5_data10",
4873+
"vin5_data12",
4874+
"vin5_data16",
4875+
"vin5_high8",
4876+
"vin5_sync",
4877+
"vin5_field",
4878+
"vin5_clkenb",
4879+
"vin5_clk",
4880+
};
4881+
46404882
static const struct sh_pfc_function pinmux_functions[] = {
46414883
SH_PFC_FUNCTION(audio_clk),
46424884
SH_PFC_FUNCTION(avb),
@@ -4696,6 +4938,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
46964938
SH_PFC_FUNCTION(usb2),
46974939
SH_PFC_FUNCTION(usb30),
46984940
SH_PFC_FUNCTION(usb31),
4941+
SH_PFC_FUNCTION(vin4),
4942+
SH_PFC_FUNCTION(vin5),
46994943
};
47004944

47014945
static const struct pinmux_cfg_reg pinmux_config_regs[] = {

‎drivers/pinctrl/renesas/pfc-r8a779g0.c

Lines changed: 56 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -206,66 +206,66 @@
206206
#define GPSR5_0 FM(AVB2_AVTP_PPS)
207207

208208
/* GPSR 6 */
209-
#define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16)
210-
#define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12)
211-
#define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8)
212-
#define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4)
213-
#define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0)
214-
#define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28)
215-
#define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24)
216-
#define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20)
217-
#define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16)
218-
#define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12)
219-
#define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8)
220-
#define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4)
221-
#define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0)
222-
#define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28)
223-
#define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24)
224-
#define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20)
225-
#define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16)
226-
#define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12)
227-
#define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8)
228-
#define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4)
229-
#define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0)
209+
#define GPSR6_20 F_(AVB1_TXCREFCLK, IP2SR6_19_16)
210+
#define GPSR6_19 F_(AVB1_RD3, IP2SR6_15_12)
211+
#define GPSR6_18 F_(AVB1_TD3, IP2SR6_11_8)
212+
#define GPSR6_17 F_(AVB1_RD2, IP2SR6_7_4)
213+
#define GPSR6_16 F_(AVB1_TD2, IP2SR6_3_0)
214+
#define GPSR6_15 F_(AVB1_RD0, IP1SR6_31_28)
215+
#define GPSR6_14 F_(AVB1_RD1, IP1SR6_27_24)
216+
#define GPSR6_13 F_(AVB1_TD0, IP1SR6_23_20)
217+
#define GPSR6_12 F_(AVB1_TD1, IP1SR6_19_16)
218+
#define GPSR6_11 F_(AVB1_AVTP_CAPTURE, IP1SR6_15_12)
219+
#define GPSR6_10 F_(AVB1_AVTP_PPS, IP1SR6_11_8)
220+
#define GPSR6_9 F_(AVB1_RX_CTL, IP1SR6_7_4)
221+
#define GPSR6_8 F_(AVB1_RXC, IP1SR6_3_0)
222+
#define GPSR6_7 F_(AVB1_TX_CTL, IP0SR6_31_28)
223+
#define GPSR6_6 F_(AVB1_TXC, IP0SR6_27_24)
224+
#define GPSR6_5 F_(AVB1_AVTP_MATCH, IP0SR6_23_20)
225+
#define GPSR6_4 F_(AVB1_LINK, IP0SR6_19_16)
226+
#define GPSR6_3 F_(AVB1_PHY_INT, IP0SR6_15_12)
227+
#define GPSR6_2 F_(AVB1_MDC, IP0SR6_11_8)
228+
#define GPSR6_1 F_(AVB1_MAGIC, IP0SR6_7_4)
229+
#define GPSR6_0 F_(AVB1_MDIO, IP0SR6_3_0)
230230

231231
/* GPSR7 */
232-
#define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16)
233-
#define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12)
234-
#define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8)
235-
#define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4)
236-
#define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0)
237-
#define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28)
238-
#define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24)
239-
#define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20)
240-
#define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16)
241-
#define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12)
242-
#define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8)
243-
#define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4)
244-
#define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0)
245-
#define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28)
246-
#define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24)
247-
#define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20)
248-
#define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16)
249-
#define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12)
250-
#define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8)
251-
#define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4)
252-
#define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0)
232+
#define GPSR7_20 F_(AVB0_RX_CTL, IP2SR7_19_16)
233+
#define GPSR7_19 F_(AVB0_RXC, IP2SR7_15_12)
234+
#define GPSR7_18 F_(AVB0_RD0, IP2SR7_11_8)
235+
#define GPSR7_17 F_(AVB0_RD1, IP2SR7_7_4)
236+
#define GPSR7_16 F_(AVB0_TX_CTL, IP2SR7_3_0)
237+
#define GPSR7_15 F_(AVB0_TXC, IP1SR7_31_28)
238+
#define GPSR7_14 F_(AVB0_MDIO, IP1SR7_27_24)
239+
#define GPSR7_13 F_(AVB0_MDC, IP1SR7_23_20)
240+
#define GPSR7_12 F_(AVB0_RD2, IP1SR7_19_16)
241+
#define GPSR7_11 F_(AVB0_TD0, IP1SR7_15_12)
242+
#define GPSR7_10 F_(AVB0_MAGIC, IP1SR7_11_8)
243+
#define GPSR7_9 F_(AVB0_TXCREFCLK, IP1SR7_7_4)
244+
#define GPSR7_8 F_(AVB0_RD3, IP1SR7_3_0)
245+
#define GPSR7_7 F_(AVB0_TD1, IP0SR7_31_28)
246+
#define GPSR7_6 F_(AVB0_TD2, IP0SR7_27_24)
247+
#define GPSR7_5 F_(AVB0_PHY_INT, IP0SR7_23_20)
248+
#define GPSR7_4 F_(AVB0_LINK, IP0SR7_19_16)
249+
#define GPSR7_3 F_(AVB0_TD3, IP0SR7_15_12)
250+
#define GPSR7_2 F_(AVB0_AVTP_MATCH, IP0SR7_11_8)
251+
#define GPSR7_1 F_(AVB0_AVTP_CAPTURE, IP0SR7_7_4)
252+
#define GPSR7_0 F_(AVB0_AVTP_PPS, IP0SR7_3_0)
253253

254254
/* GPSR8 */
255-
#define GPSR8_13 F_(GP8_13, IP1SR8_23_20)
256-
#define GPSR8_12 F_(GP8_12, IP1SR8_19_16)
257-
#define GPSR8_11 F_(SDA5, IP1SR8_15_12)
258-
#define GPSR8_10 F_(SCL5, IP1SR8_11_8)
259-
#define GPSR8_9 F_(SDA4, IP1SR8_7_4)
260-
#define GPSR8_8 F_(SCL4, IP1SR8_3_0)
261-
#define GPSR8_7 F_(SDA3, IP0SR8_31_28)
262-
#define GPSR8_6 F_(SCL3, IP0SR8_27_24)
263-
#define GPSR8_5 F_(SDA2, IP0SR8_23_20)
264-
#define GPSR8_4 F_(SCL2, IP0SR8_19_16)
265-
#define GPSR8_3 F_(SDA1, IP0SR8_15_12)
266-
#define GPSR8_2 F_(SCL1, IP0SR8_11_8)
267-
#define GPSR8_1 F_(SDA0, IP0SR8_7_4)
268-
#define GPSR8_0 F_(SCL0, IP0SR8_3_0)
255+
#define GPSR8_13 F_(GP8_13, IP1SR8_23_20)
256+
#define GPSR8_12 F_(GP8_12, IP1SR8_19_16)
257+
#define GPSR8_11 F_(SDA5, IP1SR8_15_12)
258+
#define GPSR8_10 F_(SCL5, IP1SR8_11_8)
259+
#define GPSR8_9 F_(SDA4, IP1SR8_7_4)
260+
#define GPSR8_8 F_(SCL4, IP1SR8_3_0)
261+
#define GPSR8_7 F_(SDA3, IP0SR8_31_28)
262+
#define GPSR8_6 F_(SCL3, IP0SR8_27_24)
263+
#define GPSR8_5 F_(SDA2, IP0SR8_23_20)
264+
#define GPSR8_4 F_(SCL2, IP0SR8_19_16)
265+
#define GPSR8_3 F_(SDA1, IP0SR8_15_12)
266+
#define GPSR8_2 F_(SCL1, IP0SR8_11_8)
267+
#define GPSR8_1 F_(SDA0, IP0SR8_7_4)
268+
#define GPSR8_0 F_(SCL0, IP0SR8_3_0)
269269

270270
/* SR0 */
271271
/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */

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