|
| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,imx-weim.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: i.MX Wireless External Interface Module (WEIM) |
| 8 | + |
| 9 | +maintainers: |
| 10 | + |
| 11 | + - Sascha Hauer <[email protected]> |
| 12 | + |
| 13 | +description: |
| 14 | + The term "wireless" does not imply that the WEIM is literally an interface |
| 15 | + without wires. It simply means that this module was originally designed for |
| 16 | + wireless and mobile applications that use low-power technology. The actual |
| 17 | + devices are instantiated from the child nodes of a WEIM node. |
| 18 | + |
| 19 | +properties: |
| 20 | + $nodename: |
| 21 | + pattern: "^memory-controller@[0-9a-f]+$" |
| 22 | + |
| 23 | + compatible: |
| 24 | + oneOf: |
| 25 | + - enum: |
| 26 | + - fsl,imx1-weim |
| 27 | + - fsl,imx27-weim |
| 28 | + - fsl,imx50-weim |
| 29 | + - fsl,imx51-weim |
| 30 | + - fsl,imx6q-weim |
| 31 | + - items: |
| 32 | + - enum: |
| 33 | + - fsl,imx31-weim |
| 34 | + - fsl,imx35-weim |
| 35 | + - const: fsl,imx27-weim |
| 36 | + - items: |
| 37 | + - enum: |
| 38 | + - fsl,imx6sx-weim |
| 39 | + - fsl,imx6ul-weim |
| 40 | + - const: fsl,imx6q-weim |
| 41 | + |
| 42 | + "#address-cells": |
| 43 | + const: 2 |
| 44 | + |
| 45 | + "#size-cells": |
| 46 | + const: 1 |
| 47 | + |
| 48 | + reg: |
| 49 | + maxItems: 1 |
| 50 | + |
| 51 | + clocks: |
| 52 | + maxItems: 1 |
| 53 | + |
| 54 | + interrupts: |
| 55 | + maxItems: 1 |
| 56 | + |
| 57 | + ranges: true |
| 58 | + |
| 59 | + fsl,weim-cs-gpr: |
| 60 | + $ref: /schemas/types.yaml#/definitions/phandle |
| 61 | + description: | |
| 62 | + Phandle to the system General Purpose Register controller that contains |
| 63 | + WEIM CS GPR register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0] |
| 64 | + should be set up as one of the following 4 possible values depending on |
| 65 | + the CS space configuration. |
| 66 | +
|
| 67 | + IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3 |
| 68 | + --------------------------------------------- |
| 69 | + 05 128M 0M 0M 0M |
| 70 | + 033 64M 64M 0M 0M |
| 71 | + 0113 64M 32M 32M 0M |
| 72 | + 01111 32M 32M 32M 32M |
| 73 | +
|
| 74 | + In case that the property is absent, the reset value or what bootloader |
| 75 | + sets up in IOMUXC_GPR1[11:0] will be used. |
| 76 | +
|
| 77 | + fsl,burst-clk-enable: |
| 78 | + type: boolean |
| 79 | + description: |
| 80 | + The presence of this property indicates that the weim bus should operate |
| 81 | + in Burst Clock Mode. |
| 82 | + |
| 83 | + fsl,continuous-burst-clk: |
| 84 | + type: boolean |
| 85 | + description: |
| 86 | + Make Burst Clock to output continuous clock. Without this option Burst |
| 87 | + Clock will output clock only when necessary. |
| 88 | + |
| 89 | +patternProperties: |
| 90 | + "^.*@[0-7],[0-9a-f]+$": |
| 91 | + type: object |
| 92 | + description: Devices attached to chip selects are represented as subnodes. |
| 93 | + $ref: fsl,imx-weim-peripherals.yaml |
| 94 | + additionalProperties: true |
| 95 | + required: |
| 96 | + - fsl,weim-cs-timing |
| 97 | + |
| 98 | +required: |
| 99 | + - compatible |
| 100 | + - reg |
| 101 | + - clocks |
| 102 | + - "#address-cells" |
| 103 | + - "#size-cells" |
| 104 | + - ranges |
| 105 | + |
| 106 | +allOf: |
| 107 | + - if: |
| 108 | + properties: |
| 109 | + compatible: |
| 110 | + not: |
| 111 | + contains: |
| 112 | + enum: |
| 113 | + - fsl,imx50-weim |
| 114 | + - fsl,imx6q-weim |
| 115 | + then: |
| 116 | + properties: |
| 117 | + fsl,weim-cs-gpr: false |
| 118 | + fsl,burst-clk-enable: false |
| 119 | + - if: |
| 120 | + not: |
| 121 | + required: |
| 122 | + - fsl,burst-clk-enable |
| 123 | + then: |
| 124 | + properties: |
| 125 | + fsl,continuous-burst-clk: false |
| 126 | + - if: |
| 127 | + properties: |
| 128 | + compatible: |
| 129 | + contains: |
| 130 | + const: fsl,imx1-weim |
| 131 | + then: |
| 132 | + patternProperties: |
| 133 | + "^.*@[0-7],[0-9a-f]+$": |
| 134 | + properties: |
| 135 | + fsl,weim-cs-timing: |
| 136 | + items: |
| 137 | + items: |
| 138 | + - description: CSxU |
| 139 | + - description: CSxL |
| 140 | + - if: |
| 141 | + properties: |
| 142 | + compatible: |
| 143 | + contains: |
| 144 | + enum: |
| 145 | + - fsl,imx27-weim |
| 146 | + - fsl,imx31-weim |
| 147 | + - fsl,imx35-weim |
| 148 | + then: |
| 149 | + patternProperties: |
| 150 | + "^.*@[0-7],[0-9a-f]+$": |
| 151 | + properties: |
| 152 | + fsl,weim-cs-timing: |
| 153 | + items: |
| 154 | + items: |
| 155 | + - description: CSCRxU |
| 156 | + - description: CSCRxL |
| 157 | + - description: CSCRxA |
| 158 | + - if: |
| 159 | + properties: |
| 160 | + compatible: |
| 161 | + contains: |
| 162 | + enum: |
| 163 | + - fsl,imx50-weim |
| 164 | + - fsl,imx51-weim |
| 165 | + - fsl,imx6q-weim |
| 166 | + - fsl,imx6sx-weim |
| 167 | + - fsl,imx6ul-weim |
| 168 | + then: |
| 169 | + patternProperties: |
| 170 | + "^.*@[0-7],[0-9a-f]+$": |
| 171 | + properties: |
| 172 | + fsl,weim-cs-timing: |
| 173 | + items: |
| 174 | + items: |
| 175 | + - description: CSxGCR1 |
| 176 | + - description: CSxGCR2 |
| 177 | + - description: CSxRCR1 |
| 178 | + - description: CSxRCR2 |
| 179 | + - description: CSxWCR1 |
| 180 | + - description: CSxWCR2 |
| 181 | + |
| 182 | +additionalProperties: false |
| 183 | + |
| 184 | +examples: |
| 185 | + - | |
| 186 | + memory-controller@21b8000 { |
| 187 | + compatible = "fsl,imx6q-weim"; |
| 188 | + reg = <0x021b8000 0x4000>; |
| 189 | + clocks = <&clks 196>; |
| 190 | + #address-cells = <2>; |
| 191 | + #size-cells = <1>; |
| 192 | + ranges = <0 0 0x08000000 0x08000000>; |
| 193 | + fsl,weim-cs-gpr = <&gpr>; |
| 194 | +
|
| 195 | + flash@0,0 { |
| 196 | + compatible = "cfi-flash"; |
| 197 | + reg = <0 0 0x02000000>; |
| 198 | + #address-cells = <1>; |
| 199 | + #size-cells = <1>; |
| 200 | + bank-width = <2>; |
| 201 | + fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 |
| 202 | + 0x0000c000 0x1404a38e 0x00000000>; |
| 203 | + }; |
| 204 | + }; |
0 commit comments