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kishonvijayabrahamjoergroedel
kishonvijayabraham
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joergroedel
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iommu/amd: Enable support for up to 2K interrupts per function
AMD IOMMU optionally supports up to 2K interrupts per function on newer platforms. Support for this feature is indicated through Extended Feature 2 Register (MMIO Offset 01A0h[NumIntRemapSup]). Allocate 2K IRTEs per device when this support is available. Co-developed-by: Sairaj Kodilkar <[email protected]> Signed-off-by: Sairaj Kodilkar <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Reviewed-by: Vasant Hegde <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
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3 files changed

+65
-14
lines changed

3 files changed

+65
-14
lines changed

‎drivers/iommu/amd/amd_iommu_types.h

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -112,6 +112,10 @@
112112
#define FEATURE_SNPAVICSUP_GAM(x) \
113113
(FIELD_GET(FEATURE_SNPAVICSUP, x) == 0x1)
114114

115+
#define FEATURE_NUM_INT_REMAP_SUP GENMASK_ULL(9, 8)
116+
#define FEATURE_NUM_INT_REMAP_SUP_2K(x) \
117+
(FIELD_GET(FEATURE_NUM_INT_REMAP_SUP, x) == 0x1)
118+
115119
/* Note:
116120
* The current driver only support 16-bit PASID.
117121
* Currently, hardware only implement upto 16-bit PASID
@@ -175,6 +179,9 @@
175179
#define CONTROL_GAM_EN 25
176180
#define CONTROL_GALOG_EN 28
177181
#define CONTROL_GAINT_EN 29
182+
#define CONTROL_NUM_INT_REMAP_MODE 43
183+
#define CONTROL_NUM_INT_REMAP_MODE_MASK 0x03
184+
#define CONTROL_NUM_INT_REMAP_MODE_2K 0x01
178185
#define CONTROL_EPH_EN 45
179186
#define CONTROL_XT_EN 50
180187
#define CONTROL_INTCAPXT_EN 51
@@ -309,14 +316,13 @@
309316
#define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
310317
#define DTE_IRQ_REMAP_ENABLE 1ULL
311318

312-
/*
313-
* AMD IOMMU hardware only support 512 IRTEs despite
314-
* the architectural limitation of 2048 entries.
315-
*/
316319
#define DTE_INTTABLEN_MASK (0xfULL << 1)
317320
#define DTE_INTTABLEN_VALUE_512 9ULL
318321
#define DTE_INTTABLEN_512 (DTE_INTTABLEN_VALUE_512 << 1)
319322
#define MAX_IRQS_PER_TABLE_512 BIT(DTE_INTTABLEN_VALUE_512)
323+
#define DTE_INTTABLEN_VALUE_2K 11ULL
324+
#define DTE_INTTABLEN_2K (DTE_INTTABLEN_VALUE_2K << 1)
325+
#define MAX_IRQS_PER_TABLE_2K BIT(DTE_INTTABLEN_VALUE_2K)
320326

321327
#define PAGE_MODE_NONE 0x00
322328
#define PAGE_MODE_1_LEVEL 0x01
@@ -847,6 +853,7 @@ struct iommu_dev_data {
847853
struct device *dev;
848854
u16 devid; /* PCI Device ID */
849855

856+
unsigned int max_irqs; /* Maximum IRQs supported by device */
850857
u32 max_pasids; /* Max supported PASIDs */
851858
u32 flags; /* Holds AMD_IOMMU_DEVICE_FLAG_<*> */
852859
int ats_qdep;

‎drivers/iommu/amd/init.c

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1060,7 +1060,8 @@ static bool __copy_device_table(struct amd_iommu *iommu)
10601060
int_tab_len = old_devtb[devid].data[2] & DTE_INTTABLEN_MASK;
10611061
if (irq_v && (int_ctl || int_tab_len)) {
10621062
if ((int_ctl != DTE_IRQ_REMAP_INTCTL) ||
1063-
(int_tab_len != DTE_INTTABLEN_512)) {
1063+
(int_tab_len != DTE_INTTABLEN_512 &&
1064+
int_tab_len != DTE_INTTABLEN_2K)) {
10641065
pr_err("Wrong old irq remapping flag: %#x\n", devid);
10651066
memunmap(old_devtb);
10661067
return false;
@@ -2736,6 +2737,17 @@ static void iommu_enable_irtcachedis(struct amd_iommu *iommu)
27362737
iommu->irtcachedis_enabled ? "disabled" : "enabled");
27372738
}
27382739

2740+
static void iommu_enable_2k_int(struct amd_iommu *iommu)
2741+
{
2742+
if (!FEATURE_NUM_INT_REMAP_SUP_2K(amd_iommu_efr2))
2743+
return;
2744+
2745+
iommu_feature_set(iommu,
2746+
CONTROL_NUM_INT_REMAP_MODE_2K,
2747+
CONTROL_NUM_INT_REMAP_MODE_MASK,
2748+
CONTROL_NUM_INT_REMAP_MODE);
2749+
}
2750+
27392751
static void early_enable_iommu(struct amd_iommu *iommu)
27402752
{
27412753
iommu_disable(iommu);
@@ -2748,6 +2760,7 @@ static void early_enable_iommu(struct amd_iommu *iommu)
27482760
iommu_enable_ga(iommu);
27492761
iommu_enable_xt(iommu);
27502762
iommu_enable_irtcachedis(iommu);
2763+
iommu_enable_2k_int(iommu);
27512764
iommu_enable(iommu);
27522765
amd_iommu_flush_all_caches(iommu);
27532766
}
@@ -2804,6 +2817,7 @@ static void early_enable_iommus(void)
28042817
iommu_enable_ga(iommu);
28052818
iommu_enable_xt(iommu);
28062819
iommu_enable_irtcachedis(iommu);
2820+
iommu_enable_2k_int(iommu);
28072821
iommu_set_device_table(iommu);
28082822
amd_iommu_flush_all_caches(iommu);
28092823
}

‎drivers/iommu/amd/iommu.c

Lines changed: 39 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2394,8 +2394,14 @@ static struct iommu_device *amd_iommu_probe_device(struct device *dev)
23942394
}
23952395

23962396
out_err:
2397+
23972398
iommu_completion_wait(iommu);
23982399

2400+
if (FEATURE_NUM_INT_REMAP_SUP_2K(amd_iommu_efr2))
2401+
dev_data->max_irqs = MAX_IRQS_PER_TABLE_2K;
2402+
else
2403+
dev_data->max_irqs = MAX_IRQS_PER_TABLE_512;
2404+
23992405
if (dev_is_pci(dev))
24002406
pci_prepare_ats(to_pci_dev(dev), PAGE_SHIFT);
24012407

@@ -3076,6 +3082,13 @@ static void iommu_flush_irt_and_complete(struct amd_iommu *iommu, u16 devid)
30763082
raw_spin_unlock_irqrestore(&iommu->lock, flags);
30773083
}
30783084

3085+
static inline u8 iommu_get_int_tablen(struct iommu_dev_data *dev_data)
3086+
{
3087+
if (dev_data && dev_data->max_irqs == MAX_IRQS_PER_TABLE_2K)
3088+
return DTE_INTTABLEN_2K;
3089+
return DTE_INTTABLEN_512;
3090+
}
3091+
30793092
static void set_dte_irq_entry(struct amd_iommu *iommu, u16 devid,
30803093
struct irq_remap_table *table)
30813094
{
@@ -3090,7 +3103,7 @@ static void set_dte_irq_entry(struct amd_iommu *iommu, u16 devid,
30903103
new &= ~DTE_IRQ_PHYS_ADDR_MASK;
30913104
new |= iommu_virt_to_phys(table->table);
30923105
new |= DTE_IRQ_REMAP_INTCTL;
3093-
new |= DTE_INTTABLEN_512;
3106+
new |= iommu_get_int_tablen(dev_data);
30943107
new |= DTE_IRQ_REMAP_ENABLE;
30953108
WRITE_ONCE(dte->data[2], new);
30963109

@@ -3171,13 +3184,14 @@ static inline size_t get_irq_table_size(unsigned int max_irqs)
31713184
}
31723185

31733186
static struct irq_remap_table *alloc_irq_table(struct amd_iommu *iommu,
3174-
u16 devid, struct pci_dev *pdev)
3187+
u16 devid, struct pci_dev *pdev,
3188+
unsigned int max_irqs)
31753189
{
31763190
struct irq_remap_table *table = NULL;
31773191
struct irq_remap_table *new_table = NULL;
31783192
struct amd_iommu_pci_seg *pci_seg;
31793193
unsigned long flags;
3180-
int order = get_order(get_irq_table_size(MAX_IRQS_PER_TABLE));
3194+
int order = get_order(get_irq_table_size(max_irqs));
31813195
int nid = iommu && iommu->dev ? dev_to_node(&iommu->dev->dev) : NUMA_NO_NODE;
31823196
u16 alias;
31833197

@@ -3239,13 +3253,14 @@ static struct irq_remap_table *alloc_irq_table(struct amd_iommu *iommu,
32393253
}
32403254

32413255
static int alloc_irq_index(struct amd_iommu *iommu, u16 devid, int count,
3242-
bool align, struct pci_dev *pdev)
3256+
bool align, struct pci_dev *pdev,
3257+
unsigned long max_irqs)
32433258
{
32443259
struct irq_remap_table *table;
32453260
int index, c, alignment = 1;
32463261
unsigned long flags;
32473262

3248-
table = alloc_irq_table(iommu, devid, pdev);
3263+
table = alloc_irq_table(iommu, devid, pdev, max_irqs);
32493264
if (!table)
32503265
return -ENODEV;
32513266

@@ -3256,7 +3271,7 @@ static int alloc_irq_index(struct amd_iommu *iommu, u16 devid, int count,
32563271

32573272
/* Scan table for free entries */
32583273
for (index = ALIGN(table->min_index, alignment), c = 0;
3259-
index < MAX_IRQS_PER_TABLE;) {
3274+
index < max_irqs;) {
32603275
if (!iommu->irte_ops->is_allocated(table, index)) {
32613276
c += 1;
32623277
} else {
@@ -3526,6 +3541,14 @@ static void fill_msi_msg(struct msi_msg *msg, u32 index)
35263541
msg->data = index;
35273542
msg->address_lo = 0;
35283543
msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW;
3544+
/*
3545+
* The struct msi_msg.dest_mode_logical is used to set the DM bit
3546+
* in MSI Message Address Register. For device w/ 2K int-remap support,
3547+
* this is bit must be set to 1 regardless of the actual destination
3548+
* mode, which is signified by the IRTE[DM].
3549+
*/
3550+
if (FEATURE_NUM_INT_REMAP_SUP_2K(amd_iommu_efr2))
3551+
msg->arch_addr_lo.dest_mode_logical = true;
35293552
msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
35303553
}
35313554

@@ -3588,6 +3611,8 @@ static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
35883611
struct amd_ir_data *data = NULL;
35893612
struct amd_iommu *iommu;
35903613
struct irq_cfg *cfg;
3614+
struct iommu_dev_data *dev_data;
3615+
unsigned long max_irqs;
35913616
int i, ret, devid, seg, sbdf;
35923617
int index;
35933618

@@ -3606,14 +3631,17 @@ static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
36063631
if (!iommu)
36073632
return -EINVAL;
36083633

3634+
dev_data = search_dev_data(iommu, devid);
3635+
max_irqs = dev_data ? dev_data->max_irqs : MAX_IRQS_PER_TABLE_512;
3636+
36093637
ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
36103638
if (ret < 0)
36113639
return ret;
36123640

36133641
if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
36143642
struct irq_remap_table *table;
36153643

3616-
table = alloc_irq_table(iommu, devid, NULL);
3644+
table = alloc_irq_table(iommu, devid, NULL, max_irqs);
36173645
if (table) {
36183646
if (!table->min_index) {
36193647
/*
@@ -3634,9 +3662,11 @@ static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
36343662
bool align = (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI);
36353663

36363664
index = alloc_irq_index(iommu, devid, nr_irqs, align,
3637-
msi_desc_to_pci_dev(info->desc));
3665+
msi_desc_to_pci_dev(info->desc),
3666+
max_irqs);
36383667
} else {
3639-
index = alloc_irq_index(iommu, devid, nr_irqs, false, NULL);
3668+
index = alloc_irq_index(iommu, devid, nr_irqs, false, NULL,
3669+
max_irqs);
36403670
}
36413671

36423672
if (index < 0) {

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