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| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Renesas R-Car MIPI DSI/CSI-2 Encoder |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Laurent Pinchart <[email protected]> |
| 11 | + |
| 12 | +description: | |
| 13 | + This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas |
| 14 | + R-Car V3U SoC. The encoder can operate in either DSI or CSI-2 mode, with up |
| 15 | + to four data lanes. |
| 16 | +
|
| 17 | +properties: |
| 18 | + compatible: |
| 19 | + enum: |
| 20 | + - renesas,r8a779a0-dsi-csi2-tx # for V3U |
| 21 | + |
| 22 | + reg: |
| 23 | + maxItems: 1 |
| 24 | + |
| 25 | + clocks: |
| 26 | + items: |
| 27 | + - description: Functional clock |
| 28 | + - description: DSI (and CSI-2) functional clock |
| 29 | + - description: PLL reference clock |
| 30 | + |
| 31 | + clock-names: |
| 32 | + items: |
| 33 | + - const: fck |
| 34 | + - const: dsi |
| 35 | + - const: pll |
| 36 | + |
| 37 | + power-domains: |
| 38 | + maxItems: 1 |
| 39 | + |
| 40 | + resets: |
| 41 | + maxItems: 1 |
| 42 | + |
| 43 | + ports: |
| 44 | + $ref: /schemas/graph.yaml#/properties/ports |
| 45 | + |
| 46 | + properties: |
| 47 | + port@0: |
| 48 | + $ref: /schemas/graph.yaml#/properties/port |
| 49 | + description: Parallel input port |
| 50 | + |
| 51 | + port@1: |
| 52 | + $ref: /schemas/graph.yaml#/$defs/port-base |
| 53 | + unevaluatedProperties: false |
| 54 | + description: DSI/CSI-2 output port |
| 55 | + |
| 56 | + properties: |
| 57 | + endpoint: |
| 58 | + $ref: /schemas/media/video-interfaces.yaml# |
| 59 | + unevaluatedProperties: false |
| 60 | + |
| 61 | + properties: |
| 62 | + data-lanes: |
| 63 | + minItems: 1 |
| 64 | + maxItems: 4 |
| 65 | + |
| 66 | + required: |
| 67 | + - data-lanes |
| 68 | + |
| 69 | + required: |
| 70 | + - port@0 |
| 71 | + - port@1 |
| 72 | + |
| 73 | +required: |
| 74 | + - compatible |
| 75 | + - reg |
| 76 | + - clocks |
| 77 | + - power-domains |
| 78 | + - resets |
| 79 | + - ports |
| 80 | + |
| 81 | +additionalProperties: false |
| 82 | + |
| 83 | +examples: |
| 84 | + - | |
| 85 | + #include <dt-bindings/clock/r8a779a0-cpg-mssr.h> |
| 86 | + #include <dt-bindings/power/r8a779a0-sysc.h> |
| 87 | +
|
| 88 | + dsi0: dsi-encoder@fed80000 { |
| 89 | + compatible = "renesas,r8a779a0-dsi-csi2-tx"; |
| 90 | + reg = <0xfed80000 0x10000>; |
| 91 | + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; |
| 92 | + clocks = <&cpg CPG_MOD 415>, |
| 93 | + <&cpg CPG_CORE R8A779A0_CLK_DSI>, |
| 94 | + <&cpg CPG_CORE R8A779A0_CLK_CP>; |
| 95 | + clock-names = "fck", "dsi", "pll"; |
| 96 | + resets = <&cpg 415>; |
| 97 | +
|
| 98 | + ports { |
| 99 | + #address-cells = <1>; |
| 100 | + #size-cells = <0>; |
| 101 | +
|
| 102 | + port@0 { |
| 103 | + reg = <0>; |
| 104 | + dsi0_in: endpoint { |
| 105 | + remote-endpoint = <&du_out_dsi0>; |
| 106 | + }; |
| 107 | + }; |
| 108 | +
|
| 109 | + port@1 { |
| 110 | + reg = <1>; |
| 111 | + dsi0_out: endpoint { |
| 112 | + data-lanes = <1 2>; |
| 113 | + remote-endpoint = <&sn65dsi86_in>; |
| 114 | + }; |
| 115 | + }; |
| 116 | + }; |
| 117 | + }; |
| 118 | +... |
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