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Merge patch series "riscv: Add vendor extensions support for SiFive"
Cyan Yang <[email protected]> says: This patch set adds four vendor-specific ISA extensions from SiFive: "xsfvqmaccdod", "xsfvqmaccqoq", "xsfvfnrclipxfqf", and "xsfvfwmaccqqq". Additionally, a new hwprobe key, RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0, has been added to query which SiFive vendor extensions are supported on the current platform. Signed-off-by: Cyan Yang <[email protected]> Link: https://lore.kernel.org/r/[email protected] * b4-shazam-merge: riscv: hwprobe: Add SiFive xsfvfwmaccqqq vendor extension riscv: hwprobe: Document SiFive xsfvfwmaccqqq vendor extension riscv: Add SiFive xsfvfwmaccqqq vendor extension dt-bindings: riscv: Add xsfvfwmaccqqq ISA extension description riscv: hwprobe: Add SiFive xsfvfnrclipxfqf vendor extension riscv: hwprobe: Document SiFive xsfvfnrclipxfqf vendor extension riscv: Add SiFive xsfvfnrclipxfqf vendor extension dt-bindings: riscv: Add xsfvfnrclipxfqf ISA extension description riscv: hwprobe: Add SiFive vendor extension support and probe for xsfqmaccdod and xsfqmaccqoq riscv: hwprobe: Document SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions riscv: Add SiFive xsfvqmaccdod and xsfvqmaccqoq vendor extensions dt-bindings: riscv: Add xsfvqmaccdod and xsfvqmaccqoq ISA extension description Signed-off-by: Palmer Dabbelt <[email protected]>
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‎Documentation/arch/riscv/hwprobe.rst

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@@ -335,3 +335,25 @@ The following keys are defined:
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* :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which
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represents the size of the Zicbom block in bytes.
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* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0`: A bitmask containing the
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sifive vendor extensions that are compatible with the
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:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
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* SIFIVE
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* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD`: The Xsfqmaccdod vendor
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extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
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Extensions Specification.
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* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`: The Xsfqmaccqoq vendor
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extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
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Instruction Extensions Specification.
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* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`: The Xsfvfnrclipxfqf
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vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged
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Clip Instructions Extensions Specification.
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* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq
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vendor extension is supported in version 1.0 of Matrix Multiply Accumulate
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Instruction Extensions Specification.

‎Documentation/devicetree/bindings/riscv/extensions.yaml

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@@ -662,6 +662,31 @@ properties:
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Registers in the AX45MP datasheet.
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https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
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# SiFive
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- const: xsfvqmaccdod
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description:
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SiFive Int8 Matrix Multiplication Extensions Specification.
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See more details in
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https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification
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- const: xsfvqmaccqoq
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description:
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SiFive Int8 Matrix Multiplication Extensions Specification.
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See more details in
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https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification
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- const: xsfvfnrclipxfqf
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description:
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SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification.
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See more details in
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https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions
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- const: xsfvfwmaccqqq
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description:
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SiFive Matrix Multiply Accumulate Instruction Extensions Specification.
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See more details in
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https://www.sifive.com/document-file/matrix-multiply-accumulate-instruction
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# T-HEAD
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- const: xtheadvector
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description:

‎arch/riscv/Kconfig.vendor

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@@ -16,6 +16,19 @@ config RISCV_ISA_VENDOR_EXT_ANDES
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If you don't know what to do here, say Y.
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endmenu
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menu "SiFive"
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config RISCV_ISA_VENDOR_EXT_SIFIVE
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bool "SiFive vendor extension support"
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select RISCV_ISA_VENDOR_EXT
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default y
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help
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Say N here if you want to disable all SiFive vendor extension
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support. This will cause any SiFive vendor extensions that are
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requested by hardware probing to be ignored.
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If you don't know what to do here, say Y.
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endmenu
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menu "T-Head"
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config RISCV_ISA_VENDOR_EXT_THEAD
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bool "T-Head vendor extension support"

‎arch/riscv/include/asm/hwprobe.h

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#include <uapi/asm/hwprobe.h>
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#define RISCV_HWPROBE_MAX_KEY 12
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#define RISCV_HWPROBE_MAX_KEY 13
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static inline bool riscv_hwprobe_key_is_valid(__s64 key)
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{
@@ -22,6 +22,7 @@ static inline bool hwprobe_key_is_bitmask(__s64 key)
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case RISCV_HWPROBE_KEY_IMA_EXT_0:
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case RISCV_HWPROBE_KEY_CPUPERF_0:
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case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0:
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case RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0:
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return true;
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}
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‎arch/riscv/include/asm/vendor_extensions/sifive.h

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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_SIFIVE_H
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#define _ASM_RISCV_VENDOR_EXTENSIONS_SIFIVE_H
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#include <asm/vendor_extensions.h>
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#include <linux/types.h>
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#define RISCV_ISA_VENDOR_EXT_XSFVQMACCDOD 0
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#define RISCV_ISA_VENDOR_EXT_XSFVQMACCQOQ 1
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#define RISCV_ISA_VENDOR_EXT_XSFVFNRCLIPXFQF 2
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#define RISCV_ISA_VENDOR_EXT_XSFVFWMACCQQQ 3
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extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_sifive;
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#endif

‎arch/riscv/include/asm/vendor_extensions/sifive_hwprobe.h

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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_SIFIVE_HWPROBE_H
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#define _ASM_RISCV_VENDOR_EXTENSIONS_SIFIVE_HWPROBE_H
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#include <linux/cpumask.h>
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#include <uapi/asm/hwprobe.h>
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#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE
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void hwprobe_isa_vendor_ext_sifive_0(struct riscv_hwprobe *pair, const struct cpumask *cpus);
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#else
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static inline void hwprobe_isa_vendor_ext_sifive_0(struct riscv_hwprobe *pair,
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const struct cpumask *cpus)
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{
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pair->value = 0;
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}
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#endif
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#endif

‎arch/riscv/include/uapi/asm/hwprobe.h

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#define RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED 4
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#define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 11
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#define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE 12
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#define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0 13
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/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
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/* Flags */

‎arch/riscv/include/uapi/asm/vendor/sifive.h

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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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#define RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD (1 << 0)
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#define RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ (1 << 1)
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#define RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF (1 << 2)
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#define RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ (1 << 3)

‎arch/riscv/kernel/sys_hwprobe.c

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#include <asm/uaccess.h>
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#include <asm/unistd.h>
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#include <asm/vector.h>
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#include <asm/vendor_extensions/sifive_hwprobe.h>
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#include <asm/vendor_extensions/thead_hwprobe.h>
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#include <vdso/vsyscall.h>
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pair->value = riscv_timebase;
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break;
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case RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0:
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hwprobe_isa_vendor_ext_sifive_0(pair, cpus);
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break;
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case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0:
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hwprobe_isa_vendor_ext_thead_0(pair, cpus);
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break;

‎arch/riscv/kernel/vendor_extensions.c

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#include <asm/vendorid_list.h>
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#include <asm/vendor_extensions.h>
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#include <asm/vendor_extensions/andes.h>
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#include <asm/vendor_extensions/sifive.h>
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#include <asm/vendor_extensions/thead.h>
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#include <linux/array_size.h>
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#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES
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&riscv_isa_vendor_ext_list_andes,
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#endif
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#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE
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&riscv_isa_vendor_ext_list_sifive,
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#endif
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#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD
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&riscv_isa_vendor_ext_list_thead,
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#endif
@@ -45,6 +49,12 @@ bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsig
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cpu_bmap = riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap;
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break;
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#endif
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#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE
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case SIFIVE_VENDOR_ID:
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bmap = &riscv_isa_vendor_ext_list_sifive.all_harts_isa_bitmap;
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cpu_bmap = riscv_isa_vendor_ext_list_sifive.per_hart_isa_bitmap;
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break;
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#endif
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#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD
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case THEAD_VENDOR_ID:
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bmap = &riscv_isa_vendor_ext_list_thead.all_harts_isa_bitmap;

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