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ARM: dts: qcom: msm8974: Use the header with DSI phy clock IDs
Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
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arch/arm/boot/dts/qcom/qcom-msm8974.dtsi

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
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#include <dt-bindings/interconnect/qcom,msm8974.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
6+
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
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#include <dt-bindings/clock/qcom,gcc-msm8974.h>
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#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
@@ -1871,10 +1872,10 @@
18711872
<&gcc GPLL0_VOTE>,
18721873
<&gcc GPLL1_VOTE>,
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<&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
1874-
<&mdss_dsi0_phy 1>,
1875-
<&mdss_dsi0_phy 0>,
1876-
<&mdss_dsi1_phy 1>,
1877-
<&mdss_dsi1_phy 0>,
1875+
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
1876+
<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1877+
<&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
1878+
<&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
18781879
<0>,
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<0>,
18801881
<0>;
@@ -1961,8 +1962,10 @@
19611962
interrupt-parent = <&mdss>;
19621963
interrupts = <4>;
19631964

1964-
assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1965-
assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1965+
assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1966+
<&mmcc PCLK0_CLK_SRC>;
1967+
assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1968+
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
19661969

19671970
clocks = <&mmcc MDSS_MDP_CLK>,
19681971
<&mmcc MDSS_AHB_CLK>,
@@ -2032,8 +2035,10 @@
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interrupt-parent = <&mdss>;
20332036
interrupts = <4>;
20342037

2035-
assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
2036-
assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
2038+
assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
2039+
<&mmcc PCLK1_CLK_SRC>;
2040+
assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
2041+
<&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>;
20372042

20382043
clocks = <&mmcc MDSS_MDP_CLK>,
20392044
<&mmcc MDSS_AHB_CLK>,

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