Skip to content

Commit 1b04fd4

Browse files
Marc Zyngieroupton
authored andcommitted
KVM: arm64: Make TCR2_EL1 save/restore dependent on the VM features
As for other registers, save/restore of TCR2_EL1 should be gated on the feature being actually present. In the case of a nVHE hypervisor, it is perfectly fine to leave the host value in the register, as HCRX_EL2.TCREn==0 imposes that TCR2_EL1 is treated as 0. Signed-off-by: Marc Zyngier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Oliver Upton <[email protected]>
1 parent a3ee9ce commit 1b04fd4

File tree

1 file changed

+13
-2
lines changed

1 file changed

+13
-2
lines changed

arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -55,14 +55,25 @@ static inline bool ctxt_has_s1pie(struct kvm_cpu_context *ctxt)
5555
return kvm_has_feat(kern_hyp_va(vcpu->kvm), ID_AA64MMFR3_EL1, S1PIE, IMP);
5656
}
5757

58+
static inline bool ctxt_has_tcrx(struct kvm_cpu_context *ctxt)
59+
{
60+
struct kvm_vcpu *vcpu;
61+
62+
if (!cpus_have_final_cap(ARM64_HAS_TCR2))
63+
return false;
64+
65+
vcpu = ctxt_to_vcpu(ctxt);
66+
return kvm_has_feat(kern_hyp_va(vcpu->kvm), ID_AA64MMFR3_EL1, TCRX, IMP);
67+
}
68+
5869
static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
5970
{
6071
ctxt_sys_reg(ctxt, SCTLR_EL1) = read_sysreg_el1(SYS_SCTLR);
6172
ctxt_sys_reg(ctxt, CPACR_EL1) = read_sysreg_el1(SYS_CPACR);
6273
ctxt_sys_reg(ctxt, TTBR0_EL1) = read_sysreg_el1(SYS_TTBR0);
6374
ctxt_sys_reg(ctxt, TTBR1_EL1) = read_sysreg_el1(SYS_TTBR1);
6475
ctxt_sys_reg(ctxt, TCR_EL1) = read_sysreg_el1(SYS_TCR);
65-
if (cpus_have_final_cap(ARM64_HAS_TCR2))
76+
if (ctxt_has_tcrx(ctxt))
6677
ctxt_sys_reg(ctxt, TCR2_EL1) = read_sysreg_el1(SYS_TCR2);
6778
ctxt_sys_reg(ctxt, ESR_EL1) = read_sysreg_el1(SYS_ESR);
6879
ctxt_sys_reg(ctxt, AFSR0_EL1) = read_sysreg_el1(SYS_AFSR0);
@@ -138,7 +149,7 @@ static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
138149
write_sysreg_el1(ctxt_sys_reg(ctxt, CPACR_EL1), SYS_CPACR);
139150
write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR0_EL1), SYS_TTBR0);
140151
write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR1_EL1), SYS_TTBR1);
141-
if (cpus_have_final_cap(ARM64_HAS_TCR2))
152+
if (ctxt_has_tcrx(ctxt))
142153
write_sysreg_el1(ctxt_sys_reg(ctxt, TCR2_EL1), SYS_TCR2);
143154
write_sysreg_el1(ctxt_sys_reg(ctxt, ESR_EL1), SYS_ESR);
144155
write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR0_EL1), SYS_AFSR0);

0 commit comments

Comments
 (0)