@@ -32,22 +32,21 @@ struct div4_clk {
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const char * name ;
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unsigned int reg ;
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unsigned int shift ;
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- int flags ;
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};
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static struct div4_clk div4_clks [] = {
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- { "i" , CPG_FRQCRA , 20 , CLK_ENABLE_ON_INIT },
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- { "zg" , CPG_FRQCRA , 16 , CLK_ENABLE_ON_INIT },
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- { "b" , CPG_FRQCRA , 8 , CLK_ENABLE_ON_INIT },
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- { "m1" , CPG_FRQCRA , 4 , CLK_ENABLE_ON_INIT },
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- { "hp" , CPG_FRQCRB , 4 , 0 },
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- { "hpp" , CPG_FRQCRC , 20 , 0 },
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- { "usbp" , CPG_FRQCRC , 16 , 0 },
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- { "s" , CPG_FRQCRC , 12 , 0 },
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- { "zb" , CPG_FRQCRC , 8 , 0 },
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- { "m3" , CPG_FRQCRC , 4 , 0 },
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- { "cp" , CPG_FRQCRC , 0 , 0 },
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- { NULL , 0 , 0 , 0 },
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+ { "i" , CPG_FRQCRA , 20 },
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+ { "zg" , CPG_FRQCRA , 16 },
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+ { "b" , CPG_FRQCRA , 8 },
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+ { "m1" , CPG_FRQCRA , 4 },
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+ { "hp" , CPG_FRQCRB , 4 },
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+ { "hpp" , CPG_FRQCRC , 20 },
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+ { "usbp" , CPG_FRQCRC , 16 },
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+ { "s" , CPG_FRQCRC , 12 },
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+ { "zb" , CPG_FRQCRC , 8 },
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+ { "m3" , CPG_FRQCRC , 4 },
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+ { "cp" , CPG_FRQCRC , 0 },
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+ { NULL , 0 , 0 },
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};
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static const struct clk_div_table div4_div_table [] = {
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